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Learn From The Experts
Here you can find demonstration videos of ASIP Designer methodology and use cases.
Overview
Introduction ¨C An Introduction to Domain-Specific Processors, and ASIP Designer (Presentation, 35 min)
Tmotion ¨C An ASIP Designer Demonstration (Tutorial, 1h 15 min)
Tsec ¨C An ASIP for Post-Quantum Cryptography (Case Study, 35 min)
Tmatch ¨C A Flexible Stereo Image Matching Accelerator Designed with ASIP Designer (Case Study, 44 min)
MMSE ¨C An Accelerator for 5G New Radio MMSE Equalization using Cholesky Decomposition (Case Study, 42 min)
An Introduction to Domain-Specific Processors, and ASIP Designer
Watch this video to get introduced to Synopsys ASIP Designer, its technology, the market trends and the ASIP Designer adoption in the market. Starting from a single processor specification, designers immediately obtain an optimizing C/C++ compiler, cycle-accurate simulator and synthesizable hardware implementation of the ASIP. Using a unique compiler-in-the-loop? and synthesis-in-the-loop? methodology, the ISA and microarchitecture can be tuned quickly to the application domain.
Watch NowTmotion ¨C An ASIP Designer Demonstration
English
In this tutorial we give a once-over-lightly tour of ASIP Designer¡¯s compiler-in-the-loop? and synthesis-in-the-loop? design methodology showing the tool at work, by the example of successively building an accelerator for a motion estimation application. Starting from a plain RISC microprocessor, in five design steps we gradually extend the architecture by adding specialized instructions, data-level parallelism and instruction-level parallelism, and special-purpose memory. At each step we profile the impact on performance and area.
Watch NowTsec ¨C An ASIP for Post-Quantum Cryptography
In this video we present a case study that demonstrates the methodology to extend a RISC-V baseline model into an ASIP for Post-Quantum Cryptography. Kyber, the first standardized key encryption mechanism designed to withstand attacks with future powerful quantum computers, is computationally very demanding due to extensive use of hashing, for example. In this case study, an ASIP optimized for accelerating Kyber was developed, starting from an open-source implementation compiled and profiled on a RISC-V base model with 2-issue VLIW and DSP extensions, and gradually adding architectural specializations that go beyond simple RISC-V extension mechanisms. The result of this moderate design effort is Tsec, an example ASIP with about 8x speed-up compared to the baseline, at 80% area increase.
Watch NowTmatch ¨C A Flexible Stereo Image Matching Accelerator Designed with ASIP Designer
English
In this video we document an advanced case study featuring the development of an accelerator for stereo image matching, while showing the tool at work. A RISC-V baseline architecture is gradually extended into a highly parallel and specialized ASIP optimized for this application. Stereo image matching algorithms are very demanding in respect of processing power (about 30 TMACs/s). We optimized the application code and co-developed the optimized instructions at high level. Using the compiler-in-the-loop? flow offered by ASIP Designer we easily verified the correctness of the application code and evaluated the performance impact. Within a few weeks we explored multiple efficient implementation solutions and made performance vs. cost tradeoffs. The result of this design effort is Tmatch, a highly specialized vector ASIP with limited ILP. The ASIP features design techniques enabling the reuse of partial computed results and multiple specialized memories in parallel with specialized addressing modes.
Watch NowMMSE - An Accelerator for 5G New Radio MMSE Equalization using Cholesky Decomposition
English
In this video we document an advanced case study featuring the development of an accelerator for 5G NR channel equalization, while showing the tool at work. A DLX RISC baseline architecture is gradually extended into a highly parallel and specialized ASIP optimized for this application. 5G New Radio (NR) channel equalization algorithms are very demanding in respect of processing power (several TMAC/s), requiring a huge number of complex-number MAC operations in combination with high memory bandwidth and quite irregular memory access patterns. In this case study, customized instructions and datapaths were added to a baseline RISC design in a stepwise approach. Multiple implementation solutions and their performance-versus-cost tradeoffs were explored with fast turnaround, using the compiler-in-the-loop? and synthesis-in-the-loop? optimization flows of ASIP Designer. The resulting design is a highly specialized ASIP featuring custom instructions, data level parallelism (SIMD), instruction level parallelism (ILP), and multicore context, which optimally balances the datapath with the memory bandwidth, and the SIMD size with the number of cores.
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