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Synopsys ZeBu? emulation systems deliver the performance needed to make verification teams and software developers working on the most advanced chips successful. Synopsys ZeBu emulation systems are modular, allowing users to deploy the capacity needed in a scalable and easily extensible fashion. Synopsys ZeBu emulation enables users to tackle SoC verification tasks earlier, including:

1. Software Bring-up

Early development and bring-up of embedded software applications on complex SoCs is a significant challenge driving the growing deployment of Synopsys ZeBu. It allows running the actual software on the emulated full-chip SoC model, or in a Hybrid Emulation mode where a processor subsystem model is running the software on a host server, further accelerating the operating system boot. The most critical element in this use model is the ability to debug and validate correct interaction of the software with the hardware, facilitated through the support of common embedded software debuggers and the industry leading Synopsys Verdi? automated debug system for the hardware.

2. Power Verification

For power validation the user will validate that power domain on/off switching is executing correctly by compiling the design including IEEE 1801 UPF-defined power domain definitions for execution within any of the Synopsys ZeBu emulation systems. For power analysis Synopsys ZeBu Empower enables multiple iterations per day with actionable power profiling in the context of the full design and its software workload. The power profiles can be used by software and hardware designers to identify substantial power improvement opportunities for dynamic and leakage power much earlier. Synopsys ZeBu Empower also feeds forward power critical blocks and time windows into Synopsys PrimePower? to accelerate RTL power analysis and gate-level power signoff.

3. Performance Validation

Allows the user to validate that the design is achieving its performance targets.  With cycle accurate mapping of the RTL to the emulation system, the user can measure latencies on critical design paths and interfaces to ensure software execution speeds are sufficient and mission critical deadlines are met. 

4. Virtualization

Emulation deployment efficiency is highest when many different users can run different design size and workloads controlled by a scheduling system. Virtualization of the emulation environment using high-performance Transactors enables this use model.

5. Virtual Host

Complex SoCs, such as AI chips, interface with CPU-based systems for task interaction and control. Virtual Host enables to execute these CPU-based systems on a virtual machine running on Synopsys ZeBu host server providing a fully transparent programming environment for the software development team.

6. Simulation Acceleration

Through integration with Synopsys VCS?, simulation acceleration enables the verification of block and platform level IP to be accelerated. Comprehensive testing using protocol specific Synopsys Verification IP and the full visibility of the Synopsys Verdi automated debug system maximizes your verification throughput.

7. Virtual Network Tester

Modern Ethernet systems with interface speeds of up to 800 Gbit/s and port counts of 256 and more can be effectively verified using  connected to the Synopsys ZeBu fast emulator.

8. Interoperability Testing

SoC teams need to validate their design in the real world environment, including plug and play testing. These real interfaces are enabled with easy to use, small form factor speed adaptor systems adapting real world data speeds to the emulation execution or they are provided with protocol interface cards working at real interface speeds.

9. Protocol IP Certification

IP development teams need to be able to certify new IP according to the standardization body requirements. They require at-speed traffic from real devices which can be tested with prototyping and protocol interface cards containing actual PHY chips for new IP standards.

Conclusion

In conclusion, Synopsys ZeBu? emulation systems provide a comprehensive solution for chip development teams, enabling early SoC verification tasks, software bring-up, power and performance validation, virtualization, and simulation acceleration. It ensures design meets performance targets, identifies power improvement opportunities, and enhances emulation deployment efficiency. Additionally, its capabilities to verify modern Ethernet systems and facilitate protocol IP certification make it an invaluable tool in the realm of advanced chip development.