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Embracing Software Modeling in Chip Design

Ed Sperling's article "" highlights an evolving trend in chip design. Chipmakers are increasingly adopting use case modeling techniques to better understand the interplay between software and hardware, particularly focusing on system performance and energy efficiency.

The Complexity of Multicore SoCs and the Role of KPIs

As multicore System on Chips (SoCs) become more software-intensive, the interactions within them grow more complex. For system designers and SoC architects, early prediction of their product¡¯s performance against rigorous application requirements is key. To achieve this, system-level goals need to be quantified using ¡°Key Performance Indicators¡± (KPIs). KPIs are vital for defining system requirements clearly and concisely, especially from the application use case perspective. Common KPI examples include:

• Frames per second for visual applications.
• I/O operations per second in storage applications like SSDs.
• Browser launch time in mobile processors and client systems.
• Pages per minute for multi-function printers.
• These KPIs serve as precise benchmarks for meeting system-level deadlines, crucial for delivering the desired user experience.

Case Study: Analyzing Browser Use Case in Synopsys Platform Architect

An example is shown in the next graphic, where three different SoC architecture configurations are simulated in Synopsys Platform Architect. All simulations use the same workload model - a task graph of the Chrome Browser in an Android environment. The charts depict CPU load over time for the browser use case, with each color indicating the load from an individual Android process. The data shows how adding processing resources improves the system's ability to execute the browser task. Importantly, the results also indicate where system optimization can further reduce power and cost while still meeting KPIs.

Conclusion

In sum, leveraging Key Performance Indicators, use case workload modeling, and early architecture analysis is crucial. This approach helps in closing the loop on specifications for next-generation architectures, ensuring that they meet the set performance standards and deadlines.