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With the announcement last week of the PCIe 6.0 high-speed interface specification¡ª64 GT/s¡ªthe design starts are imminent. But if you are looking for something that is deploying with great performance and bandwidth along with a nascent ecosystem that will support it, the PCIe 5.0 specification at 32 GT/s doesn¡¯t disappoint. In fact, over 200 Synopsys PCIe 5.0 IP licenses have been sold to date, proving that PCIe 5.0 designs are currently in massive deployment and making PCIe 5.0 a smart choice for your designs today. The application possibilities for using PCIe high-speed interface to connect your components are far-ranging: re-timers, cloud-based computing servers, solid-state drives (SSDs), and automotive, to name a few. Anything where huge amounts of data are being crunched. 

Speed and bandwidth are not your only considerations. As with everything, reward often comes with some risk. And as you evaluate your risk-reward tradeoff in making the leap to the next generation of PCI Express, we wanted to highlight a few things about PCIe 5.0 for you to consider.

PCIe Gen 5 Is Deploying, but Choose Your IP Partners Wisely

To mitigate your risks, it¡¯s a good idea to work with IP that is silicon-proven from a vendor that has deep expertise in PCIe. A good indicator that our IP is on track to achieve certification from PCI-SIG, for instance, is the sheer volume of our PCIe 5.0 IP adoption to date. Surpassing 200 licenses is a milestone and an endorsement, if you are looking to make your move to PCIe 5.0 ahead of the official PCI-SIG integrators¡¯ list. (And by the way, the first PCI-SIG integrators list for PCIe 5.0 is expected sometime in the coming months, so stay tuned.)

You can also inquire about a vendor¡¯s past PCI-SIG certifications. Synopsys has silicon-proven IP with production volume well over a billion units and the most PCI-SIG certifications of any IP vendor with more interoperability testing, including extensive hardware validation platforms, proven within the ecosystem. We perform rigorous design verification and have the preeminently proven PHY and controller on the market, and were the first vendor with integrated security IDE IP for PCIe 5.0. Our deep PCIe technical expertise includes the industry¡¯s foremost PCIe experts on staff, with key contributors to the PCI-SIG specification, multiple PCI-SIG working group members, and a member of the PCI-SIG board of directors.

Some of the successes in the PCIe 5.0 ecosystem include:

A notable example that PCIe 5.0 is on the rise was the launch of Intel¡¯s next-generation Xeon server processor, . Sapphire Rapids is a PCIe 5.0-enabled CPU launched in 2021 with production expected in the . This processor will help drive adoption of PCIe 5.0 and expand the ecosystem. As the first to interoperate with Intel¡¯s Sapphire Rapids, we are also the world¡¯s first to demonstrate a complete end-to-end PCIe 5.0-enabled system in hardware. 

We are working together with IBM to double AI compute performance every year for the next decade. Silicon verification and demonstrable performance improvements have already been realized. One example of this includes a high-performance data center rack (Figure 1), which connects the processor with the accelerator, the flash controller, the re-timer, the CXL switches, and the SSDs. Having the right PCIe 5.0 IP is foundational for interoperability and conductivity between the entire system. 

Figure 1. Having the right PCIe 5.0 IP for this high-performance computing data center rack is foundational for interoperability and conductivity within the entire system.

When you build a re-timer for a NIC card or a storage device, it¡¯s difficult to launch the PCIe 5.0 32-GT/s signals across long backplanes and be able to receive them without corruption. To combat this, Astera Labs uses our DesignWare? Controller and PHY IP, putting a chip between the launching and receiving end of the signal where it¡¯s cleaned up and moved forward to prevent the corruption. With high-bandwidth, high-speed standards, re-timers are more important than ever. 

Why is all of this a big deal? 

While there still is some risk inherent in the newness of PCIe 5.0, these indicators of success all add up. It makes designing in PCIe 5.0 a good bet. It tells you that the risk¡ªwhile not completely gone¡ªis diminishing. It tells you that PCIe 5.0 designs are happening. The ecosystem is growing. And there are credible, experienced resources out there that can help. All of this can give you a sense of ease choosing the PCIe 5.0 standard for your next design.  

Reward: Maximum Throughput and Security with Minimum Latency and Power

While we still see a lot of use cases for PCIe 4.0, the rise of PCIe 5.0 is here, and it will soon be mainstream while the early adopters are already making their move toward PCIe 6.0. There¡¯s a lot to consider in the risk-reward tradeoff as you decide what¡¯s right for your design. After all, you want your silicon to work on the first pass. You want your product to be interoperable. You want your customers¡¯ data to be secure. You don¡¯t want bugs or problems requiring silicon respins. Partnering right is important. It¡¯s the only way to achieve the rewards that PCIe 5.0 promises¡ªmaximum throughput and security, minimum latency, and minimum power in a small area. Silicon-proven IP solutions, deep PCIe and security expertise, and an extensive winning track record in your IP partners will not only reduce your risk, it will help you throttle up for a whole new generation of application complexity and speed. Learn about PCIe and Security IDEs.