Synopsys Cloud
Cloud native EDA tools & pre-optimized hardware platforms
Request a Free Trial →
Table of Contents
PCI Express? (PCIe?) is the serial interconnect that is ubiquitous for connecting our Smart Everything world, from solid state drives in the datacenter to computing on the edge. And the latest update to the specification, PCIe 6.0.1, just dropped on Tuesday. To take advantage of all that PCIe has to offer in the latest generation of the specification, make sure your ecosystem partners support the PCIe 6.0.1 update before you tape out. And if you use Synopsys IP and protocol verification solutions, then you won¡¯t have to think twice about it. Our IP and protocol verification solutions already support PCIe 6.0.1, enabling you to leverage all the advantages of this specification today, including:
- Data transfer rates at 64 GT/s per pin
- Greater power and cost efficiency
- High-performance integrity
- Data encryption
- Backwards compatibility to older versions of the specification
- New PAM-4 electrical signaling modulation scheme
- New package structure supporting higher bandwidth
- Sleeping state for flexibility and low power
- Data integrity and security protections
Why Trusted Partners Matter
As the complexity of SoC design increases and the world becomes more interconnected, trusted partners with deep experience are important to keep your products on the leading edge with lower risk. Synopsys is at the head of the pack in PCIe know-how because we lead in PCI-SIG certifications among any IP vendor and our security experts actively contribute to the PCI-SIG specification. There¡¯s also widespread adoption of our PCIe solutions. Our PCIe verification solutions are first in the market and provide end-to-end protocol verification closure from IP to SoC to multi-die systems using simulation, emulation, and prototyping platforms.
If you want to get started today with PCIe 6.0.1 check out our Synopsys Controller IP for PCIe 6.0 with MultiStream architecture, Synopsys IDE Security IP Module, Synopsys PHY (available on FinFET processes), and our Verification IP that uses native System/Verilog UVM architecture for acceleration of testbench development. For a deeper dive on PCIe 6.0.1 check out our article: What¡¯s New in PCIe 6.0¡ªBeyond the Bandwidth.