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Analog Fault Simulation using Synopsys Custom Design Platform

Kai Wang, Director of Engineering at Synopsys, introduces analog fault simulation and explains how Synopsys TestMAX CustomFault enables full-chip functional safety and test coverage analysis.

Transcript:

Hello, everyone. Welcome to the second video whitepaper in our series on custom reliability. In this session, Kai Wang, our Synopsys R&D leader, will introduce you to analog fault simulation and explain how Synopsys TestMAX CustomFault enables full chip analog fault simulation for functional safety and test coverage analysis.

Analog fault simulation is part of Synopsys' complete reliability solution, which spans the full product life cycle, including early failures, radiation-induced failures, and wear-out failures. This production-proven solution is foundry certified and optimized for performance. Please go ahead, Kai.

So why do we need analog fault simulation? There are three major applications for analog fault simulation:

1. Functional Safety Verification: Analog fault simulation can be applied to aid in the analysis of a circuit's functional behavior and robustness to ensure continued safe operations.
2. Silicon Failure Analysis: When a chip fails, analog fault simulation can be used to quickly identify the root cause of the failures.
3. Manufacturing Test Coverage: Analog fault simulation can be applied to improve test coverage and reduce defect rates.

This is the overview of the fault simulation flow. It includes the following five major steps:

1. Simulation Setup: The user can set up simulation parameters through GUI and config file.
2. Fault Identification: It supports both automatic fault identification and manual fault insertion.
3. Fault Reduction: To speed up fault simulation, fault reduction is performed based on electrical and logical equivalence or weighted random sampling.
4. Parallel Simulations: After reduction, a large number of SPICE simulations are launched in parallel.
5. Reporting: Finally, it will report the test and diagnostic coverage summary and detailed fault analytics.

TestMAX CustomFault is a new high-performance analog fault simulation solution from Synopsys built on industry-leading CustomSim and FineSim simulation technology and featuring a highly differentiated feature set. TestMAX CustomFault delivers superior performance, capacity, and throughput along with easy-to-use diagnostics to make full chip test coverage analysis practical and cost-effective.

TestMAX CustomFault is built on a modular architecture that fuses industry-leading CustomSim and FineSim simulators with a powerful frontend to provide seamless fault identification, reduction, simulation, and report generation with unparalleled performance. Ease of use becomes a critical requirement as users begin to scale their fault campaigns to multiple large designs involving multiple test benches.

TestMAX CustomFault simplifies fault modeling by supporting a broad class of user-configurable fault models, including traditional short and open models for MOS, R, L, C, and BJT, as well as transient and parametric faults. TestMAX CustomFault caters to the unique diagnostics and reporting requirements of automotive, functional safety verification, and manufacturing test coverage analysis use cases.
Users can analyze the efficiency of primary and redundant safety mechanisms in mitigating failures in their safety-related hardware and generate diagnostic coverage metrics to verify industry standard reliability compliance. Thank you.

Thank you so much, Kai. That was a really insightful session. In the next video whitepaper in our series, Kai will introduce you to circuit electrical rule checking (ERC) and how Synopsys' custom design platform and its key technologies can ensure design robustness and reliability. Thank you for watching.