91³Ô¹ÏÍø

Unifying the Powers of Synthesis and Place and Route

The first RTL-to-GDSII, synthesis and place-and-route solution, enabling highly-convergent and predictable digital implementation.

Transcript:

Fusion Compiler is an exciting new RTL to GDS implementation product from Synopsis, enabling a new era in digital design. We fused best in class synthesis and sign off technologies with IC Compiler II's leading place in route technology, on a single data model and analysis back plane. The single cockpit approach offers unmatched quality of results but fast throughput to address the challenges presented by the industry's most advanced designs.

Fusion compiler is built on a single, highly scalable data model that supports synthesis, sign off analysis, and physical implementation engines. These best in class engines form a single unified optimization framework, delivering a predictable flow with up to 20% better quality of results and two times faster throughput.

Technologies previously used only in place and route can now be applied during synthesis, and vice versa, scaling new heights in timing, power, and area optimization. The new solution is the only RTL to GDS product built on an analysis backbone that is based on the industry's golden sign off tools, PrimeTime Static Timing Analysis and StarRC extraction.

Market leading semiconductor companies and early adopters have already taped out their most challenging designs with Fusion Compiler, realizing significant timing improvements and power reductions. The predictable path from synthesis to sign off has also reduced design iterations, ensuring that teams can meet their aggressive product schedules. After the first successful tape outs, early adopters are now engaged in broadly deploying Fusion Compiler on their most advanced designs.