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While decreasing process nodes deliver huge benefits in terms of circuit density and increasing compute power, there is an associated downside ¡ª increasing design variability. This variability derives from the need for margin, the guard-banding of specifications that engineers introduce to improve design robustness and reduce tapeout risks. The tighter the specifications are set, the greater the risk of failure, impacting final costs. Designers need new tools to effectively and efficiently minimize the excessive design margins they specify, thereby reducing both cost and risk.

The first of this two-part post will explore the problems facing designers working on SoCs targeting energy-efficient design, and how Synopsys¡¯ PrimeShield? technology can help optimize designs for lower power while achieving aggressive time-to-market goals.

The Reality

Semiconductors have long been specified based on worst-case process, voltage and temperature (PVT). During the design phase, designers have had to balance performance against power and area (PPA), trying to achieve the needed performance-per-watt goals. To assess the impact of variability on circuit performance, designers resort to static timing analysis (STA) to assess each timing path. Due to the many factors that can impact PPA, designers often perform SPICE simulations to achieve more accurate results.

However, as both process nodes advance and circuit density increases, there is also increasing pressure on time to market. The result is that design teams are limited in the amount of robustness analysis they can perform pre-signoff, resulting in over pessimism (increasing design margins to ensure that performance and power targets are hit). It is a truism in design and manufacturing that the earlier mistakes can be caught, or optimizations performed, the cheaper the impact ¡ª robustness improvement is no exception.

The end result of this over design is decreased robustness that directly impacts the end-product PPA, time to market, and material costs ¡ª all factors that can make a semiconductor supplier uncompetitive in the marketplace. A robust statistical robustness analysis tool that can be applied earlier in the design cycle and help improve design immunity to variation is needed.  

Enter PrimeShield: Monte Carlo on Steroids

While Monte-Carlo SPICE simulation has been the gold standard for circuit analysis, it does not scale for today's circuit densities. By their very nature, Monte Carlo simulations must repeat the same analysis thousands, or even millions of times for high-sigma accuracy, making it practical for only dozens of cells. 

PrimeShield leverages Synopsys¡¯ PrimeTime? golden signoff engine to perform SPICE-accurate timing calculations and variation modeling in seconds. To achieve the needed throughput, PrimeShield takes advantage of the repetitive nature of Monte-Carlo analysis and uses patented machine-learning technology to greatly improve analysis performance. The result is a 100 to 10,000 times improvement in analysis throughput, performing statistical simulation on critical timing paths in large-scale SoCs with billions of cells within minutes versus days or weeks as required by traditional statistical simulations.