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Efficient Top-Level Interconnect Planning and Implementation with Synopsys IC Compiler II

Jiangtao Meng, Sr. R&D Manager at Synopsys, discusses how IC Compiler II and Fusion Compiler enable intelligent planning and implementation of complex interconnects through innovative Topological Interconnect Planning (TIP) technology, to accelerate project schedules while achieving the highest performance targets that the most challenging semiconductor segments such as AI and HPC demand.

Transcript:

Hello, my name is Jiangtao. I'm from Synopsys design planning team. In this video, I will talk about the top level interconnected planning.

Today, the demand for computing power of artificial intelligence systems is doubling every few months. It requires larger and more complex chips. The number of interconnections and their complexity is significantly rising as a result, efficient top level interconnected planning becomes a very important part of the entire AI chip design flow.

Traditional interconnected planning approach involves numerous manual steps for planning, what-if analysis, iteration, and implementation. QR becomes a function of a designer's activities. Besides that, floor plan changes can get very time consuming and error prone.

Synopsys IC Compiler II and Fusion Compiler provide top level interconnect planning capability or TIP. It is a comprehensive interconnected planning system that enables intelligent planning of complex interconnections through fast exploration and implementation to achieve best overall performance for your AI designs. TIP reduces planning, optimization, and implementation turnaround time and saves weeks to months on floor plan design iterations.

To begin with, the designer plans the routing topologies by creating topology plans, which capture user intention of how these interconnections should be routed and buffered. TIP natively supports multilevel physical hierarchy and multiple instantiated blocks, which is important for AI designs. It automatically converts the topology plans into detailed constraints and helps optimize and manage multiple topology plans. Feedthroughs and pins are created. Virtual registers and repeaters are placed as needed.

Early feedback and timing analysis are available after each major step to identify any floor plan or timing issues early in the planning process. Final implementation is through push button style that fully converts the plan to physical routes, feedthroughs, pins, and real repeaters. A full-chip planning customer case study reported the reduction of four to six days per floor plan iteration where 80+ topology plans were used for a fully abutted 7-nanometer design.

This result achieved the highest level of overall chip performance with months of saving, leading to an accelerated tape-out. Distributed block implementation runtime was only 70 minutes for over 5,000 routes, with repeaters inserted, and the block came out DRC clean. As AI designs continue to grow to massive size and complexity, the TIP technology reduces interconnected routing turnaround time and saves months on floor plan iterations. TIP enables accelerated project schedules while delivering the highest performance targets your AI SOC designs demand.