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Chip designs for aerospace and defense applications like satellites, rockets, radars, and submarines need to operate reliably and securely in harsh environments. These SoCs are growing more complex, often with billions of hardware gates and thousands of lines of software code. Additionally, software and hardware are highly intertwined to deliver the lasting performance needed for critical missions.

Through customer use, we have found that the cloud is proving to be an excellent chip design and verification environment, providing the availability of virtually unlimited compute performance, elasticity, and flexibility to get the job done. One of the biggest advantages is the virtually unlimited and advanced compute resources that deliver the capacity chip designers need at peak times, such as when they are trying to meet tapeout deadlines. EDA tool flow and license management have also remained a heavy lift, and the cloud can ease the burden of that effort substantially. Finally, we are also seeing that customers find the cloud to be a great way to evaluate new tools in their already existing flows.

Against this backdrop, Synopsys is collaborating with Microsoft to improve silicon design assurance with secure, cloud-based analog and digital integrated circuit (IC) development environments. This effort is part of the  to deploy hardware design workflows that incorporate Synopsys¡¯ analog and digital design flows with added confidentiality and integrity (C&I) techniques into Microsoft¡¯s Azure government cloud infrastructure.

The idea behind the multi-phase, multi-year U.S. Department of Defense (DoD) RAMP program is to bring the innovation and speed of commercial electronic design to the development of state-of-the art (SOTA) semiconductors for DoD systems with C&I techniques employed.

Synopsys kicked off RAMP phase one by defining requirements and reference flows targeting the design and fabrication process for analog and digital chip design in the cloud, along with proposing C&I techniques for use in design and manufacturing. Synopsys and Microsoft collaborated closely to define requirements and processes for optimized deployment of EDA tools and flows on Microsoft¡¯s Azure cloud infrastructure.

 program involves using the cloud infrastructure and C&I techniques proposed in phase one to design and fabricate chips with RAMP program partners. The reference flows are developed by the Synopsys Design Services team, renowned for first-pass silicon success, and Synopsys¡¯ Custom Design and Manufacturing group, with advanced full-featured custom, analog, and photonic IC tool flows. With phase two, Synopsys is enhancing its digital and analog design and verification solutions for enterprise and cloud use, to enable trust and assurance throughout the silicon lifecycle.

Overall, phase one and two of the  augment existing SoC design practices used by DoD suppliers. The RAMP augmentations include C&I, cloud-based analog and digital design, intellectual property (IP) integration, post-design release processes, and post-manufacturing test, characterization, and verification. Synopsys and other RAMP partners are working to provide microelectronics quantifiable assurance (MQA) data whether hosted in a cloud or enterprise environment.