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About Universal Chiplet Interconnect Express

Synopsys Verification IP (VIP) for Universal Chiplet Interconnect Express (UCIe) provides verification of design implementations based on latest UCIe specifications which can be used from IP to system level to accelerate verification closure. Synopsys VIP for UCIe enables verification for all topologies and at all signaling interfaces of a UCIe design: Flit aware Die-to-Die interface (FDI) between Protocol layer and Die to Die adapter, Raw Die-to-Die Interface (RDI) between Die-to-Die adapter and Physical layer, and Physical link interface between two dies - for single and multi-module chiplet setups. Synopsys VIP Test Suites, pre-built specification tied testcases, and SoC integration setups with IPs help accelerate your time to market with high quality deliverables.

Key Benefits

Features

Highlights

  • Native SystemVerilog/UVM
  • Source code test
  • Built-in protocol checks
  • Verification plan and coverage
  • Synopsys Verdi protocol-aware debug
  • Runs on all major simulators
Category: Feature:
Specification Version UCIe 1.0, 1.1, 2.0
DUT Configuration Full Stack
D2D Adapter
PHY
Protocol
Protocol Mode Streaming Mode
CXL over UCIe
PCIe over UCIe
Interface FDI
RDI
PHY Mainband and Sideband
Package Standard (x16)
Advanced (x32, x64)?
Module Configuration Single Module
Multi Module
Link Speeds Up to 32GT/s
Link Width x16, x32, x64, x128, x256
RDI Shim Layer Interface to provide direct communication between US and DS RDI
RDI API Interface To inject user-defined Sideband and Mainband packets at RDI interface (bypassing Die-to-Die Adapter and FDI)
FDI/RDI Mainband Width 16B, 32B, 64B, 128B, 256B
FDI/RDI Sideband Width 8 bits, 16 bits, 32 bits
Registers Specification Defined registers (DVSEC, PHY/D2D, UHM)
Passive Monitors FDI
RDI
Link
D2D Adapter
PHY Features Link Initialization and training
Data, Clock and Track Lane repair
Lane reversal
Dynamic clock gating - Half rate and Quarter rate
PHY Trainings Sideband training
Mainband training
Link Initialization
PHYRETRAIN
D2D Adapter Features Protocol and Parameter negotiation
Arbitration and Muxing
Retry
CRC and parity computation
VIP Features Individual Layer granularity
Bypass LTSM states and sub-states
Enable/Disable scrambler
Configurable D2C training iteration and pattern count
Control to send Sideband packets from protocol layer to protocol layer
Debug Ports at each interface level
Error Injection Transaction corruption using callback and exceptions
Training pattern corruption at LTSM

Resources