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Ever since UCIe? (Universal Chiplet Interconnect Express?) consortium was formed and version 1.0 of the UCIe specification was released, the chiplet/die-to-die ecosystem has been frenzied. IP architects and developers have their task cut-out for them ¨C to come up with a robust design and implementation that benefits from the heterogenous system without compromising their power, performance, and area (PPA) goals. System architects and designers are busy putting the technology in their next generation SoCs. Verification teams are running against time to create test and coverage plans based on the integrated logic before they receive disintegrated chip RTL.
Let¡¯s review what we have seen in the first revision of the specification.
- Multi-layer protocol: application specific protocol layer, die-to-die adapter and physical layer
- Signalling interface between different layers
- FDI (flit-aware die-to-die interface) between protocol layer and die-to-die adapter
- RDI (raw die-to-die interface) between die-to-die adapter and physical layer
- Physical link interface between two dies
- Separate mainband and sideband interface at all the layers
- Native specifications support for CXL, PCIe and streaming protocol
- Single and multi-module in physical layer interface
While the first revision focused on features for signaling and chiplet architecture, version 1.1 addresses compliance and interoperability to support multi-vendor heterogenous systems.
Let¡¯s demystify what¡¯s happening in newly released specification.
New Features with UCIe 1.1:
- Flit mode support for streaming protocol
- CRC and retry support for streaming mode
- Stack mux on die-to-die adapter with options of two different protocols on multiplexer
- Asymmetric mode for streaming mode
- Multi module link mode
(Read our previous blog on UCIe 1.0 feature and specification details.)
What¡¯s Different between UCIe 1.0 and UCIe 1.1 Specification:
In UCIe 1.0 only raw mode was supported for streaming protocol where UCIe was used for the transport layer only, but in the UCIe 1.1 specification flit formats are added for streaming protocol. These are optional formats that allow custom protocols to use 68B/256B/256B latency optimized flit adapter capabilities. The 1.1 revision adds support for CRC detection with 3-bit detection guarantee of any random error and corresponding replay buffer to reinitiate transaction for any CRC error for streaming mode.
The 1.0 specification limited the stack mux at die-to-die adapter to use the same protocol at both multiplexor inputs but with latest revision, the stack multiplexor supports a combination of protocols in a single UCIe instance. This allows bandwidth sharing at the die-to-die adapter between these protocols. The latest revision also allows asymmetric mode in streaming mode with allowed configuration as EP (end point) or RC (root complex) through software register programming.
With independent layer design, it also requires multiple verification topologies to support end to end verification. These topologies can support the design under test (DUT) in back-to-back mode with traffic generation from test sequencers or an interop DUT and VIP connection. For system verification, the most suitable topology is a full stack implementation where all layers can be stitched together to create a complete system. A typical verification environment to support such use cases is illustrated in Figure 1. With stack mux supporting multiple protocols the verification system will encapsulate CXL, PCIe and Streaming (custom) protocol to support all use cases.
For the physical layer, version 1.1 adds capabilities for x32 pin module for advanced package, whereas version 1.0 only supported x16 and x64 pin physical layer interface.
Additional compliance and test debug registers are added for interoperability testing requirement of UCIe DUT with a reference UCIe design (golden die).
Synopsys UCIe 91³Ô¹ÏÍø:
Synopsys has been working with industry leaders to support features and use cases for latest UCIe 1.1 specification.
Synopsys¡¯ complete Universal Chiplet Interconnect Express (UCIe) IP solution includes controller, PHY and verification IP. Synopsys UCIe controller and PHY IP solutions enable robust and reliable die-to-die links with testability features for known good dies and CRC or parity checks for error correction.
Synopsys offers verification IP (VIP), test suites, and protocol solutions for hardware-assisted platforms. Leveraging Synopsys¡¯ broad interconnect portfolio, our partners can perform early verification of their Chiplet designs.
Synopsys IPs are verified using independently developed Synopsys VIPs providing companies with an industry-leading UCIe solution. A complete out-of-the-box solutions enables designers to focus on chip design features and differentiation to accelerate their time-to-market.
As the target usage for UCIe is die-to-die interconnects, the payload that the chiplet RTL requires demands faster hardware-based pre-silicon solutions. Synopsys transactors based on Synopsys IP enable fast verification hardware solutions including Synopsys ZeBu? emulation systems and Synopsys HAPS? prototyping systems for validation use-cases.
Synopsys protocol verification solutions are natively integrated with the Synopsys Verification Family of products including Synopsys Verdi? debug and regression management and automation with Synopsys VC Execution Manager.
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