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Synopsys Verification IP (VIP) for MIPI C-Phy provides a comprehensive set of protocol, methodology, and verification features, enabling users to achieve accelerated verification closure of MIPI C-Phy.

VIP is based on next generation architecture and implemented in native SystemVerilog/UVM, which eliminates the need for language translation wrappers that affects performance and ease-of-use. VIP can be integrated, configured and customized easily with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences.


Highlights

  • Native SystemVerilog/UVM and Verilog
  • Source code test suite (optional)
  • Runs natively on all major simulators
  • Built-in Protocol checks
  • Verification plan and coverage
  • Verdi? protocol analyzer
  • Error injection and exceptions

Key Features

  • Specifications: CSI-2 4.0 (CSE), CSI2 3.0, CSI-2 up to 2.1 compliant with CPHY 2.1 up to 2.0, DSI-2 v2.0, DSI-2 v1.1 compliant with C-PHY 2.1 up to 2.0
  • C-PHY Serial and Parallel (PPI) Interface
  • C-PHY Lane Distribution and Merging
  • Multi-Lane support (1 to N)
  • High Speed mode for SERIAL and Parallel Interface
  • LPDT mode support for SERIAL and Parallel Interface
  • ULPS mode support for SERIAL and Parallel Interface
  • TRIGGER mode support for SERIAL and Parallel Interface
  • LPDT pause feature
  • C-PHY Serial/PPI level Error Injection
  • Controllability of all C-PHY Global operational timing parameters
  • Run-Time reconfiguration of Dynamic Parameters
  • Support for Alternate Low Power(ALP), Concurrent ALP and Calibration
  • Support for Sync Word Sync Types
VC Verification IP for MIPI

C-PHY VIP Architecture