Cloud native EDA tools & pre-optimized hardware platforms
Synopsys Verification IP (VIP) for MIPI C-Phy provides a comprehensive set of protocol, methodology, and verification features, enabling users to achieve accelerated verification closure of MIPI C-Phy.
VIP is based on next generation architecture and implemented in native SystemVerilog/UVM, which eliminates the need for language translation wrappers that affects performance and ease-of-use. VIP can be integrated, configured and customized easily with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences.
C-PHY VIP Architecture
Contact the VIP Team