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Synopsys Verification IP (VIP) for MIPI CSI-2 (Camera Serial Interface) provides a comprehensive set of protocol, methodology, verification and productivity features enabling users to achieve rapid verification of MIPI CSI TX and RX devices. It also includes VIP for MIPI D-PHY and C-PHY for physical layer verification. CSI-2 supports data-type interleaving frames, normal frames and Virtual Channel ID interleaving frames. It simplifies testbench development by enabling engineers to use a single VIP to verify multiple transmission modes across the full CSI-2 protocol. 


Highlights

  • Native SystemVerilog/UVM and Verilog
  • Source code test suite (optional)
  • Runs natively on all major simulators
  • Built-in Protocol checks
  • Verification plan and coverage
  • Verdi? protocol analyzer
  • Error injection and exceptions

Key Features

  • Specifications: CSI-2 4.0 (CSE), CSI2 3.0, CSI-2 up to 2.1 compliant with CPHY 2.1 up to 2.0, DSI-2 v2.0, DSI-2 v1.1 compliant with C-PHY 2.1 up to 2.0
  • C-PHY Serial and Parallel (PPI) Interface
  • C-PHY Lane Distribution and Merging
  • Multi-Lane support (1 to N)
  • High Speed mode for SERIAL and Parallel Interface
  • LPDT mode support for SERIAL and Parallel Interface
  • ULPS mode support for SERIAL and Parallel Interface
  • TRIGGER mode support for SERIAL and Parallel Interface
  • LPDT pause feature
  • C-PHY Serial/PPI level Error Injection
  • Controllability of all C-PHY Global operational timing parameters
  • Run-Time reconfiguration of Dynamic Parameters
  • Support for Alternate Low Power (ALP), Concurrent ALP and Calibration
  • Support for Sync Word Sync Types
Verification IP for MIPI CSI-2

VIP Architecture