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Technology Feature: Wide scope of RISC-V ASIP models ready for ASIP accelerator development

When developing an ASIP architecture, engineering teams typically do not start from a blank sheet of paper. Often, ASIP Designer? customers start from one of the example processor models that are shipped with the tool installation. This library contains models that are based on either publicly known ISAs such as Hennessy and Patterson¡¯s DLX or the more recent RISC-V ISA, or on other ad-hoc ISAs.  The examples are there to demonstrate how to model specific architecture features such as SIMD, VLIW, floating point, multi-threading and many others.  Synopsys is continuously extending its library of ASIP example models.  For example, a wide scope of RISC-V ISA based models has been created and are frequently used by customers as a starting point to design proprietary ASIP accelerators.  Using a RISC-V ISA baseline facilitates compatibility with and reuse of existing processor ecosystem elements.

In ASIP Designer, the Trv family of processors implements the RISC-V ISA.  These models implement the base integer ISA and various ISA extensions.   In this section we will elaborate on the members of the Trv family listed in Figure 1.  All these variants are verified against reference implementations of the RISC-V ISA. They are fully supported by all components of the ASIP Designer tool suite, including C/C++ compilation, the generation of both cycle- and instruction-accurate simulation models (that can also be integrated in a virtual platform), RTL generation, and on-chip debugging.

Integer models

The integer models implement the RV32IM or RV64IM base integer instructions and multiplication extension.  They come in versions with a 32- or a 64-bit wide data path and with a three or five stage protected pipeline. Multiplications are executed on a hardwired multiplier; divisions are executed on an iterative divider unit.

These models are optimized for area and clock frequency. Depending on the configuration and on the clock frequency, the gate count ranges from 28k to 40k gates for the 32-bit variants.  For a 28nm technology, clock frequencies (Fmax) as high as 1.4 GHz can be achieved. Using the ASIP Designer compiler a performance of 3.3 CoreMark/MHz is reached.

Floating-point models

The floating-point models add the F extension instructions to the 32-bit wide data path integer models, implementing the RV32IMF ISA. Additive and multiplicative instructions are executed on a hardwired fused multiply-add unit with a throughput of one operation per clock cycle. For the 5-stage version, this unit is pipelined. Other hardwired units implement compare, min/max and conversion instructions. The floating-point division and square-root instructions are executed on a shared iterative unit.

The gate counts for these models are in the range of 55k to 90k gates. The Fmax of the 5-stage variant is 1.2 GHz (28nm).

Extended models

As mentioned, the purpose of the Trv models is to have a solid starting point for the development of an application-specific processor. ASIPs often target compute-intensive applications where arrays of data that are stored in memory must be processed.  For these type of applications, we observe that the RISC-V ISA lacks the following important features:

• A zero-overhead looping mechanism that allows to efficiently implement the loops that iterate over the arrays. 
• Load and store instructions with a post-modify addressing mode, that allow to make pointer updates without instruction overhead.
• Instruction-level parallelism to support the simultaneous execution of a compute operation and a memory access.

To provide an improved starting point for compute-intense applications, we have developed models that extend the standard RISC-V ISA with these features. These models have an <x> suffix to their name (see Figure 1). Figure 2 shows the ISA that is supported by these models. It contains:

• The standard RV32IM 32-bit instructions, encoded with the ¡°11¡± format bits at the LSB side.
• Dual issue (parallel) instructions. Slot1 supports compute operations (ALU, multiply, divide) and control operations.  Slot 2 supports load/store operations and the ability to execute a register move in parallel with a slot1 operation.  The dual-issue instructions are 64-bit wide and are encoded with the ¡°10¡± format field.
• Note that there are additional 64-bit instructions, under the ¡°00¡± format.  These are single-issue control-flow and compute instructions with a long 32-bit immediate operand.  When large constants or long jumps are present in the code, these instructions offer a more efficient alternative to the two-step approach for constant or jump-target generation that is needed when only standard RISC-V instructions are present.

SDX models

The Trv-SDX is an example processor model that implements the RISC-V ISA, and additionally contains templates for extension instructions.  These templates are encoded using the RISC-V custom-2 opcode space, which has been reserved in the standard to enable custom ISA extensions. The Trv-SDX model was covered in detail in the October 2020 ASIP eUpdate.

Tmoby model

Tmoby is an example of an application-specific processor that was designed starting from the Trv32p5 model (Figure 3). The objective was to design an accelerator for convolutional neural networks like MobileNet. We targeted medium throughput applications and decided upfront to allocate a vector data path with 64 MAC units, each capable of executing an 8x8 bit multiplication and 18-bit accumulation. The vector data path contains multiple vector register files: VEC stores a vector of 8 features, MAT stores 64 weights. The feature vector is replicated eight times and multiplied with the weights. The resulting product is added to the accumulator ACC. To sustain a throughput of one vector MAC per cycle, we need to load a new feature vector and a new weight vector each cycle. This is achieved by allocating two vector memories, VM and WM. In the ISA, we provide two loads as parallel operations to the vector MAC. The VLIW structure has a fourth slot, which hosts the RISC-V scalar instructions. With this architecture we can accelerate MobileNet V3 by a factor 360 compared to a scalar RISC-V core.