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ASIP eUpdate, December 2015
Overview
Welcome to the latest issue of the ASIP eUpdate Newsletter, our bi-annual publication to keep you informed on topics related to application-specific instruction-set processor (ASIP) design. ASIPs are a proven solution for domain-specific/application-optimized processors, plus often serve as a more flexible yet equally efficient alternative to fixed RTL implementations, often referred to as programmable accelerators.
ASIPs come with an architecture and instruction set tuned for a specific application domain. They rely on similar techniques as used in the design of hardware accelerators to reach high performance and low power: heavy use of parallelism and specialized datapath elements. Yet ASIPs retain software programmability within their application domain, resulting in C/C++ programmable processors and accelerators with the lowest power possible.
Synopsys is the leader in ASIP design solutions, offering tools, example processor models, and services. This newsletter covers the latest enhancements to ASIP Designer?, the leading ASIP tool solution, and it highlights the wide range of processor models available to jump-start your design. It shows how companies like Fuji Xerox and Conexant have successfully deployed ASIPs for very different applications. And in the methodology section, it has a more detailed look at the subject of software-development kit (SDK) creation for existing and upcoming in-house processors.
What¡¯s New in ASIP Designer?
On Dec 7th, the latest release of ASIP Designer (2015.12) became available and offers many enhancements since its release in March 2015, including
- Extended programming language support, now featuring:
- C, optionally extended with user-defined data types and operators using C++ classes and overloading
- C++ (leveraging LLVM compiler front-end technology)
- OpenCL C (OpenCL kernel language)
- Instruction set simulator (ISS) performance increase
- Important software enhancements have been made to the ISS code generated by ASIP Designer. For cycle-accurate simulations, we see the simulation performance increasing anywhere from 2x to 8x on example scalar ASIPs, and by 2x to 4x on example vector ASIPs. No modification of the nML source code is required, so you can give it a try right away.
- Stay tuned for more news on this topic, as we prepare for our March ¡¯16 release applying new technology for Just-In-Time (JIT) compilation during simulation, resulting in additional simulation speed-up (or contact us for a beta version right away).
- Integration into Virtual Prototyping flows, providing automatic SystemC wrapper generation for pin-accurate and TLM2-LT interfaces
- Eclipse debug plugin, enabling the integration into an Eclipse based IDE, as often required when building software development kits for larger subsystems
There are many more enhancements that came with the 2015.06 and 2015.12 releases. For more features and additional details about the topics listed above, please refer to the ASIP Designer release notes, send a note to asipsupport@synopsys.com, or contact your local Synopsys representative. We will be happy to arrange for a specific update presentation.
Example Processor Models
ASIP Designer comes with a large number of example processor models, provided in nML source code. These example models are an excellent way to get started. Here is a short list:
For more details on these example models, or information on additional example models, send a note to asipsupport@synopsys.com, or contact your local Synopsys representative.
Technology Feature: Using ASIP Designer to Equip Existing In-House Processors with a Quality SDK
While ASIP Designer enables architectural exploration and design of new application-specific instruction-set processors, the tool is also successfully used by companies to create a software development kit (SDK) for legacy in-house processors. Teams designing in-house processors often find that they have limited time and expertise to also create, deploy, maintain and support an SDK for their processor. By modeling the legacy processor in nML and using ASIP Designer, the time and effort needed to create the SDK can be significantly reduced, and Synopsys¡¯ deployment and support infrastructure can be leveraged.
View our new webinar on this topic: Automatically Generate A Software Development Kit for Your In-House Processor
Customer Successes
Fuji Xerox
On Sept 3rd, Fuji Xerox presented a paper at SNUG Japan entitled ¡°Implementing scanned image skew correction using an ASIP approach¡±. In this presentation Noriaki Tsuchiya, Manager at the Controller Development Group, Fuji Xerox, described how an ASIP approach allowed him to replace a number of fixed-function RTL components with software programmable accelerators, resulting in a significant area reduction without impacting the system performance. Look here for the complete success story to learn more about Fuji Xerox¡¯s use of ASIP Designer.
White papers
The following whitepapers are available for download
White paper: Rapid Architectural Exploration in Designing Application-Specific Processors
White paper: Designing ASIPs in Multicore SoCs
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Events