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Q: Can you briefly explain the concept of Fusion Compiler's Golden Signoff Backbone?

Neeraj Kaul: Fusion Compiler is at the center of a multi-year effort in creating a wholly unified  Design Platform. This unified solution, architected around a common data model, and signoff driven engines enables the seamless invocation of various optimization engines throughout the flow to deliver a hyper-convergent, signoff-accurate RTL-to-GDSII design flow. This platform's key advantage is the unique deployment of Synopsys' ¨C the industry's most trusted ¨C golden-signoff solutions as the standard reference throughout the entire design flow. 

Q: What are the solutions available in Fusion Compiler's Golden-Signoff backbone?

Neeraj Kaul: Fusion Compiler incorporates all applicable Synopsys Signoff 91³Ô¹ÏÍø, including, but not limited to, PrimeTime, PrimePower, PrimeShield, StarRC, ICV, and VCS, as well as RedHawk through our exclusive partnership with Ansys.

Q: What is the role of Synopsys' golden-signoff analysis during design implementation?

Neeraj Kaul:

Co-optimizing performance, power, and area (PPA) is the central role of design implementation, intending to ensure that the resulting design fulfills functional requirements and achieves design quality metrics such as operating frequency, thermal profiles, and chip size targets. With Synopsys' unified platform, golden-signoff analysis is the singular reference that drives all of these optimization decisions. Since optimization is driven by signoff engines,  the platform thus innately guarantees the design is optimal and signoff accurate at every step of the flow.

Q: What are the benefits of having golden-signoff analysis as the reference during optimization?

Neeraj Kaul:

First and foremost are the enhanced quality-of-results a design realizes, but also key is the reduction in total flow time to eventual signoff. As mentioned, Fusion Compiler deploys a breadth of PPA optimization techniques to address various design challenges. Typical non-signoff engines with errors on both sides,  result in  underoptimizing and overoptimizing different parts of the design. This causes  surprises at the end of the flow and loss of PPA. With Synopsys' unique approach, the platform's golden-signoff engines can correctly guide the optimization engines to focus their effort in the right places and towards the right goals by accurately representing all design metrics. Deploying signoff engines  ensures the fastest design convergence by eliminating over-/under-optimization of a design, reducing costly design iterations ¨C the dreaded ping-pong effect ¨C caused by a miscorrelation with final signoff. Traditionally designers apply pessimism on the design through margins. While this technique may reduce some surprises, it comes with a significant cost of PPA. Fusion platform golden signoff approach eliminates the need for such costly margins.

Q: Signoff correlation has always been an important consideration for digital implementation flows; how is this approach different?

Neeraj Kaul:

Signoff correlation has long been a differentiating advantage of Synopsys' digital implementation solutions due to the unique access and in-house collaboration with Synopsys' industry's most-trusted signoff solutions. Advanced nodes come with new effects which need accurate modeling for timing, power and other metrics. Traditional correlation techniques cannot keep up with the accuracy needed for advanced nodes and leave PPA on the table.   Fusion Platform has taken the correct-by-construction approach by embedding signoff engines inside the optimization loop. This eliminates the need for correlation management, thus delivering an RTL-to-GDSII design-flow architecture that is signoff accurate and delivers the best PPA.

Q: Could you elaborate on the concept of "correlate by construction?"

Neeraj Kaul:

Synopsys continuously collaborates with our leading-edge ecosystem partners to innovate and front-run the upcoming challenges in the chip-design space. With each introduction of new process nodes or technologies, emerging trends and new analysis technologies are developed that ensure accurate signoff. Fusion Compiler directly and immediately absorbs these latest signoff technologies through the common platform approach. It can thus deliver signoff-correct results without additional patch-build work or other delays in release. This software architecture ensures the implementation and signoff engines are always identical at the code level and thus correlated by construction.

Q: While "correlate by construction" sounds like a significant technology advantage, could you explain why it is essential for designers?

Neeraj Kaul:

Our customers often tell us that signoff analysis is incomplete without an accompanying optimization technology. In addition to achieving the fastest design convergence through proper signoff correlation, this platform approach ensures that any new signoff metric introduced in the signoff space is readily optimized during implementation. One recent example of this is the Vmin analysis concept introduced by PrimeShield. Vmin analysis offers a significant opportunity to reduce total power ¨C particularly the dynamic power component ¨C which has become increasingly critical for High-performance computing (HPC) targeted designs. Thanks to the platform approach, Fusion Compiler's power optimization flows were immediately  driven by PrimeShield's Vmin analysis to explore new PPA-gain opportunities. The lag between signoff and implementation is eliminated.

Q: Signoff analysis is accurate but usually compute intensive. How does the golden-signoff backbone impact total design turnaround time?

Neeraj Kaul:

Accurate signoff analysis indeed takes more computation than fast heuristics. Synopsys' state-of-the-art signoff engines have been architected to be highly scalable and efficiently balance speed and accuracy trade-offs during the various implementation phases. Furthermore, Fusion Compiler deploys Machine-learning-driven techniques from physical synthesis to signoff closure that leverages machine prediction whenever applicable to speed up the optimization-solution-space exploration by orders of magnitude. With faster design convergence and a reduced number of iterations, our customers consistently see faster time-to-results from RTL to signoff.

Q: What can we expect next for the golden-signoff backbone in Fusion Compiler?

Neeraj Kaul:

The golden-signoff backbone represents a major component in our hyper-convergent design platform. Fusion Compiler has already adeptly demonstrated the benefits of having common engines, in this case, the signoff engines, on this unified platform. However, we have aggressive ongoing ambitions to expand the interleaving of signoff technologies in Fusion Compiler and the complete RTL-to-GDSII design flow. By way of example, advanced technologies such as PrimeShield's Vmin analysis that I mentioned earlier, PrimeShield's fast, Monte-Carlo statistical engine, as well as PrimeTime's nascent, HyperTrace technology are all potential candidates for deployment consideration. These highly differentiated technologies, being effectively leveraged beyond their obvious role of facilitating better signoff correlation, will be used to advance Fusion Compiler's PPA to previously unattainable levels. I look forward to sharing more as they come closer to productization.

About the Author

Neeraj Kaul is a VP of Engineering at Synopsys leading the Fusion Platform Engineering team covering the full solution from RTL to GDS. He has over 25 years of experience in developing and managing rapid, large scale EDA software development from concept to customer deployment.  Neeraj received his B.S. from IIT Delhi, Master¡¯s and Ph.D in Electrical Engineering from Vanderbilt University.