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Even as chips continue to grow more complex, there remains a constant demand to get these silicon products out to market faster. Application areas like high-performance computing (HPC), artificial intelligence (AI), 5G, automotive, as well as GPUs are placing pressure on chip designers to deliver billion-gate designs with the processing performance, bandwidth, latency, and power needed for these applications to thrive. And even automotive design cycles for the SoCs are nowadays approaching these fast time-to-market requirements.
Given this environment, chip designers are looking to design and verification tools to do more in less time. Electronic design automation (EDA) vendors are responding with robust offerings to help engineers find and fix problems earlier in the design cycle. SoC emulation systems are one area where we¡¯re seeing continued innovation. In this blog post, I¡¯ll center our discussion on software bring-up and hardware and system verification, with a focus on the increasingly important role of fast chip emulation.
How Can You Quickly Find the Root Cause of Failures?
The two primary options for hardware and software verification each have their advantages:
- Emulation systems support fully automated flows, with speeds much faster than those of simulators along with the ability to provide full-visibility debug
- Prototyping systems are generally faster than emulators, allowing investigation of much longer application workloads, while requiring more effort for the user to achieve this
In a typical verification, there¡¯s room for both types of systems. Emulation is ideal when a design isn¡¯t quite as mature, while prototyping can be done when the design is very mature in order to quickly find corner cases. There¡¯s been a desire in the industry, however, for emulation systems to push performance much higher, while maintaining their debug and automation advantages.
Debug is one of the most time-consuming aspects of verification. Verification engineers report spending roughly 41% of their time on debug, according to the . Yet the importance of this painstaking effort cannot be minimized, given that the earlier you can find and fix bugs, the less costly it is to your design and your overall budget. The fact that, in our exascale debug era, only exacerbates the debug throughput challenge. SoCs for the application areas we¡¯ve discussed, such as HPC and AI, fall into this bucket. Along with this software complexity and growing SoC sizes are factors such as the increase in chip-to-chip and external communication requirements¡ªall of which are making the case for faster, more powerful emulation systems.
Emulation plays an essential role in debugging and validating the correct interaction of the software with the hardware in a chip design. By quickly zeroing in on root causes of test failures, so you can get a jump on resolving the issues, emulation can do its part to accelerate the chip design and verification process.
10-MHz SoC Emulation in a Single Platform
It is in this high-pressure environment that electronics companies have continued to invest in fast emulation and prototyping farms, providing the foundation to accelerate software bring-up, SoC verification, and system validation. However, not all verification systems are the same. In some cases, you need to purchase an emulation system and a prototyping system for the same hardware verification flow, switching between the two for hardware debug and for software validation. While these two systems may promise a common compile and testbench approach, it still entails the costs of procuring and maintaining two systems. And from a workflow perspective, it brings the need to manage simultaneous jobs from different projects on two platforms.
A better approach for verification plus software bring-up is to use a single emulation system that runs much faster. With one platform, you can use a common reservation system to run all of your jobs for a more effective debug schedule. You also have the flexibility of investing in the capacity you need, rather than being saddled with investing in two systems. Synopsys provides all of these advantages with our ZeBu? EP1 emulation system, the industry¡¯s first 10-MHz emulation solution that is ideal for SoC designs of up to 2 billion gates. The system is based on a direct-connect architecture between the FPGAs in the system, minimizing processing delays and delivering high performance. ZeBu EP1 also provides:
- System-level debug including fast waveform output
- The industry¡¯s lowest total cost of ownership, factoring in operational expenses like cooling and electricity as well as the overall lower overhead of running a single system
- High reliability, as proven by the Synopsys track record of ZeBu emulation systems
ZeBu EP1 provides the capacity and performance for SoCs in areas such as automotive, 5G infrastructure, AI at the edge, and HPC (even if a full HPC SoC is too large for the system, ZeBu EP1 can support its large IP blocks). The ZeBu family of products is part of the Synopsys Verification Continuum? of solutions that is designed to help find SoC bugs earlier and faster, bring-up software earlier, and validate the entire system.
Summary
Remember back in the ¡®90s, when hardware emulators began growing in popularity but were expensive and difficult to use? At that point in time, no one would have imagined that with fast emulation systems it is possible to run 1-trillion-cycle application workloads. That¡¯s what users of ZeBu EP1 today have already accomplished. If its current evolutionary path is any indication, fast emulation will remain a critical force, helping engineers tackle SoC verification, software bring-up, and system validation challenges as they push the limits of Moore¡¯s law.