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Q: Welcome Vineet. Synopsys recently unveiled RTL Architect. Can you tell us more about the motivation for this new product and its significance?

Vineet Rashingkar:

Certainly. We have seen over the last few years that increasing complexities of advanced process nodes has made it much harder for design teams to achieve their PPA goals. In addition, the emergence of new market verticals such as AI and automotive require customers to do early and rapid architecture exploration to meet the PPA targets. This challenge of deriving best PPA has moved upstream in the RTL-to-GDSII flow and has put a lot of pressure on RTL designers to dramatically improve RTL quality prior to any implementation feedback. However, the process today is not efficient since it lacks a platform for RTL developers to accurately measure the PPA impact of their RTL modifications.

Synopsys¡¯ RTL Architect has been designed to address this RTL design closure challenge. It is the industry¡¯s first physically aware RTL analysis, optimization and signoff system, built from the ground up for superior RTL handoff. It enables RTL designers to quickly achieve superior RTL and reduces the SoC implementation cycle in half.

Q: Why is RTL Architect different than existing solutions in the market today?

Vineet Rashingkar:

Existing point tool solutions for estimating RTL quality are severely limited due to poor accuracy to downstream implementation. These early design cycle inaccuracies cause downstream tools to compensate, causing several RTL iterations in order to meet PPA goals. The fragmented solutions today are not physically aware and are optimizing for single cost functions. RTL Architect is uniquely positioned to address these challenges as it directly leverages Synopsys¡¯ world-class implementation and golden signoff solutions to deliver results that correlate-by-construction early in the design cycle.

Q: Can you elaborate on the innovative technologies in RTL Architect?

Vineet Rashingkar:

The core differentiating technology in RTL Architect is its fast, multi-dimensional Predictive Engine that enables RTL designers to predict power, performance, area, and congestion impact of their RTL changes. RTL designers can now pinpoint inefficiencies in their HDL source code and improve its quality.

RTL Architect also shares many of the technologies available in the Synopsys Digital Design Family. Specifically, the unified Fusion data model provides unprecedented capacity, scalability and comprehensive hierarchical design capabilities to address the growing needs for advanced node designs. Another key technology is the integration with Synopsys¡¯ PrimePower golden signoff power analysis engine to enable accurate RTL power estimation and optimization for energy-efficient designs.

Finally, the new product also provides RTL restructuring, constraints management and cross-probing facilities to provide early insights into key quality metrics.

Q: Who are the target users for RTL Architect?

Vineet Rashingkar:

RTL Architect benefits SoC and IP RTL designers as well as front-end implementation teams. SoC and  IP RTL designers can perform rapid architectural explorations to achieve the best design PPA and handoff implementable RTL with confidence. SoC integrators and RTL synthesis teams, on the other hand, can use RTL Architect as a checkpoint for RTL that enters the digital implementation flow.

Q: When in the RTL development cycle should customers use RTL Architect?

Vineet Rashingkar:

RTL Architect is designed to be used throughout the RTL development cycle. For example, at early stages, RTL restructuring and floorplanning features will be used more frequently. Later during the development phase, congestion, timing, and power feedback from RTL Architect can be used to tune RTL quality.

Q: How does RTL Architect fit into the Synopsys Digital Design Family?

Vineet Rashingkar:

RTL Architect is a brand-new product introduced in the Synopsys Digital Design Family to fuse boundaries that exist today between RTL developers and RTL synthesis teams. With its unique new technologies and the foundation of Synopsys¡¯ world-class engines, RTL Architect will be the gateway for entry into RTL-to-GDSII flow.

Q: Thank you Vineet for joining us for this insightful discussion on Synopsys RTL Architect. Any closing remarks?

Vineet Rashingkar:

You are welcome! We are very excited about RTL Architect. In fact, in our early engagements partners are already observing the benefit of quick, early, and accurate RTL analysis in their development cycle resulting in improved productivity. We look forward to working with our wider customer base to enable the shift-left for RTL design closure with RTL Architect.