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SoCs today incorporate various standard on-chip and off-chip communication protocols to interact with processor cores, memory subsystems, and peripherals, ranging from simple APB interfaces to complex coherent interfaces. With the extensive scope of verification required, it's more pragmatic for designers to verify these interfaces' core functionality using off-the-shelf Verification IP (VIP) and Assertion IPs (AIP).
Synopsys VIPs and AIPs are pre-verified and have been tested in numerous customer designs, ensuring compliance with standard protocols. The difference between VIP and AIP lies in their implementation and the specific advantages they offer, which complement each other for comprehensive verification. Synopsys VIP, implemented in native SystemVerilog/UVM, offers a built-in verification plan, sequences, protocol checks, and functional coverage for accelerated verification closure. Unlike VIPs, which are primarily behavioral and non-synthesizable, AIPs are implemented using SystemVerilog synthesizable assertions and cover properties, making them reusable across simulation, formal, and emulation platforms.

VIPs, consisting of standard components like driver, monitor, and scoreboard, integrate natively with Verdi protocol and performance analyzer for faster debug and performance verification. AIPs, lacking transaction-driving drivers, are not directly useful for standalone IPs in simulation but are efficient in SubSystem or SoC simulations to monitor and check interface behavior. They are instrumental in pinpointing the root cause of failures, allowing efficient debugging at higher levels with the Verdi Waveform Debugger.

The unique advantages of AIPs stem from their implementation using SystemVerilog Assertions (SVA) and bind constructs. This allows efficient instantiation in subsystems or SoCs, as an AIP bound to an AHB SystemVerilog interface, for example, automatically binds to all design instances in the SoC using that interface. Configuration through parameterization simplifies the setup, and assertions and coverage properties can be globally or selectively turned on or off.

Synopsys VC Formal customers utilize AIPs with Formal Register Verification (FRV) and Formal Property Verification (FPV) apps for exhaustive verification to unearth corner-case bugs. FRV employs AIPs to model the register interface, ensuring accurate configuration register read/write operations. FPV, through a rich set of properties in AIP, performs exhaustive verification of interface protocols, with assertions verifying protocol adherence under legal input combinations, and coverage metrics assessing effectiveness.
Once IPs are thoroughly verified in formal settings, AIPs are advanced to subsystem or SoC levels in simulation or emulation for further checks and efficient debugging. Coverage collected using AIPs can be integrated with other simulation coverage metrics and fed into the verification planner to close the verification loop.

In summary, Synopsys AIPs and VIPs assist design and verification teams in focusing on their chips' core intent while managing interface protocol concerns. VIPs, with their drivers, are versatile across IP, subsystem, and SoC level verification in simulation, whereas AIPs, pivotal in formal property verification at the IP level, subsequently aid in subsystem/SoC verification using simulation and emulation. This complementary application of VIPs and AIPs facilitates the identification of diverse bug types, ensuring a high-quality verification signoff.