DSO.ai
由人工智慧驱动的设计应用
瞭解更多 →
Elite SNUG Reference
** Require Synopsys Secure Sign In (Solvnet) to access all protected documents
Digital Implementation and Verification
- (Imp-01) Improving Timing Convergence Efficiency Combining Bottom-Up and Top-Down Methodologies
Intel
Paper Presentation
- (Imp-02) High Efficiency and Reliability ICC2 HDP Flow on 12M SOC design
Novatek
Presentation Link Coming Soon
- (Imp-03) Use ECO Fusion for Timing Closure and Galaxy Custom Routing for DDR Wire Matching Outing to Achieve Timing Closure Faster in 6M Large Flatten Design
Vatics
Presentation Link Coming Soon
- (Imp-04) RedHawk Analysis Fusion
Toshiba
Presentation Link Coming Soon
- (Imp-05) Best Practices for High-Performance, Energy Efficient Implementations of the Latest ARM Processors
Arm/Synopsys
Presentation
AMS and Custom Design
- (Ams-01) First Pass Silicon Success Using Custom Compiler
Seagate
Presentation
- (Ams-02) New Custom Design Flow with Synopsys Custom Compiler
Etron
Presentation Link Coming Soon
- (Ams-03) Development of Compatibility Flow Between Custom Compiler and Other Vendor Tools
Renesas
Presentation
- (Ams-04) Highspeed SerDes Verification with Synopsys VCS + CustomSim Co-Sim Solution
M31
Presentation Link Coming Soon
- (Ams-05) FineSim Spice S-parameter simulation in Signal Integrity Analysis
Sunplus
Presentation Link Coming Soon
- (Ams-06) A Simulation-Based Failure Rate Analysis for Automotive Applications Using CustomSim
Kilopass
Paper Presentation
Verification
- (Ver-01) Use of Synopsys Virtualizer to Shift Left Software Development of Solid State Drives
Intel
Presentation - (Ver-02) Regression Testing for Verification of Advanced CPU Subsystems using Fast Emulation
AMD/Synopsys
Presentation - (Ver-03) Using the AMBA VIP to integrate a C/C++ processor model in the RTL simulation, and debug with Verdi
NXP
Paper Presentation - (Ver-04) Formal Verification of Software Configurable Silicon for SDN
Cavium / Oski
Paper Presentation - (Ver-05) Introduction to Reset Domain Crossings
Synopsys
Presentation - (Ver-06) Extending Coverage Planning to Low Power Verification
Broadcom
Paper Presentation - (Ver-07) Glitch Scaler - A New Approach to Model Glitch Power in Logic Simulation
MediaTek USA
Paper Presentation - (Ver-08) Speed is the Name of the Game, Every Second Counts! (Simulation Acceleration Using VCS FGP Technology)
nVidia
Paper Presentation - (Ver-09) Achieving faster Testbench Development turnaround using Partition Compile
Xilinx
Paper Presentation - (Ver-10) Does ISO 26262 scale to large, complex SoCs?
nVidia
Presentation - (Ver-11) Using Synopsys Z01X to Fasten the Fault Injection Campaign of a Fully Configurable IP
Arteris IP
Paper Presentation - (Ver-12) Building Smart SoCs: Using Virtual Prototyping for the Design and SoC Integration of Artificial Intelligence Accelerators
Synopsys
Presentation