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影片集

专题影片

SMI – Success with ZeBu

Learn how SMI is using ZeBu emulation to develop storage solutions, validating firmware/drivers as well as using pre-silicon performance benchmarking to stay ahead of their competition.

Sunplus – Success with ZeBu

Sunplus is using ZeBu to support the collaboration of their world-wide teams of system engineers, software developers and RTL designers to validate their automotive and video applications.

Phison – Success with HAPS

Learn how Phison changed from in-house prototyping platforms to HAPS prototyping to achieve predictable project schedules and high efficiency debug.

训练影片

變革性的數位實作技術推動晶片设计創新新紀元

在這影片中,Synopsys研發人員將分享Fusion Compiler和ICC II最新的變革性技術,這些技術可提升可預測結果品質(QoR)的水平,並推動下一階段的晶片设计創新。

HAPS Solution Overview

Learn about HAPS FPGA prototyping, the industry’s fastest prototyping solution, to accelerate software development and HW/SW validation.

Early Power Optimization and Analysis

Learn about Synopsys’ SpyGlass Power Explorer and PowerReplay to analysis and optimize power early in the design stage. SpyGlass Power Explorer enables power estimation and optimization at the RTL stage and PowerReplay accelerates analysis for accurate power signoff.

全新的HAPS-100 FPGA Prototyping 系統介紹

此影片介紹新思科技最新的FPGA Prototyping平台,HAPS-100系統。HAPS-100使用Xilinx最新的VU19P FPGA,可以讓FPGA Prototyping有更快的performance以及更大的容量。

Verdi 偵錯秘訣

如何罢谤补肠别信号中有错误的值

追蹤信號往往花了工程師許多時間。在這支影片中我們將告訴你如何使用Verdi的Temporal Flow View (TFV)功能加快追蹤錯誤信號的時間。

如何顿别产耻驳含有低功耗描述语言鲍笔贵的电路

這支影片可以幫助你了解如何使用Verdi 來Debug電路中含有UPF低功耗描述語言。

痴颁厂-鲍濒迟谤补的顿罢尝和顿滨痴新功能介绍

這支影片介紹VCS-Ultra的Dynamic test loading (DTL) 以及 Design intent verification (DIV)兩個新功能。

如何在Verdi上讀取Exclusion File

在Coverage driven verification 中,coverage 的分數是決定验证工作是否完成的主要依據,但在許多情形下,為了讓验证工作更有效率,必需將一些不重要的事項從coverage分數排除。透過影片,我們將介紹如何使用Verdi來讀取以及管理exclusion file。

Verdi Planner 快速入門

Coverage driven verification 是現今设计验证的重要課題,利用Verdi planner的功能,你可以透過Verdi的介面快速的建立验证計畫(verification plan)。透過這支影片,可以了解如何開始使用Verdi Planner。