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Optimized for Architecture Performance and Power
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Synopsys Platform Architect models provide commonly required architectural components including generic traffic generators, interconnects, memory subsystems, and embedded processors. This enables architects and system designers to efficiently design, analyze, and optimize the performance, power, and cost of SoC architectures in Platform Architect.
Key Benefits
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Interconnect Models
Generic:?
SBL-TLM2-FT (AXI)?
SBL-GCCI (ACE)?
Arteris?:
Arteris FlexNoC & Ncore?
Arm:
Arm Performance Models?
Arm AHB/APB?
Synopsys:?
Synopsys AXI
Memory Subystems
Generic: ?
Multiport memory controller (GMPMC)?
SRAM controller?
Cache controller?
NoC?
Synopsys?:
uMCTL2 / DDR5/ LPDDR5 / HBM3 Memory Controller?
?RTL Co-simulation
Traffic, Processors, RTL
Task-based and Trace-based Workload Models?
Cycle Accurate Processor: ?
ARC?
Tensilica?
CEVA?
?RTL Co-simulation/emulation