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VC Verification IP for AMBA AHB
Synopsys? VC Verification IP for Arm? AMBA? AHB? provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of Arm AMBA based designs supporting AHB5, AHB3, AHB2, AHB-Lite, and AHB Multi Layer.
Highlights
- Native SystemVerilog/Verilog with UVM
- Optional source code Test suite (EA)
- Runs on all major simulators
- Performance metrics for latency and throughput
- Reference Verification Platform
- Built-in port and system level checks for protocol, data integrity
- Built-in verification plan and coverage
- Verdi? protocol aware debug
- Debug port for transaction tracking on waveforms
Key Features
AXI Interconnect Test Suites Available
- Complete protocol support for AHB5, AHB3, AHB2, AHB-Lite, and AHB Multi Layer
- Includes primary, secondary, monitor
- Configurable bus model
- Backdoor access to AHB secondary memory
- Ability to control wait states and secondary response types
- Ability to control signal values during idle periods