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The Synopsys SLM SHS IP Yield Accelerator extends the value of the SLM IP SHS to the test floor by addressing the need to rapidly, cost-effectively and accurately identify, analyze, isolate and classify memory faults as designs are readied for transition from first silicon to volume manufacturing. Leveraging the infrastructure of the SLM SHS IP, the SLM SHS IP Yield Accelerator automatically generates vectors for test equipment and provides fault analysis and root-cause failure guidance based on silicon test results. Using this feature, test and product engineers can rapidly analyze failures manifested in embedded memories and inspect the physical location and class of each fault to determine the root cause without involving the IP vendor or SoC designer.