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SLM Signal Integrity Monitor (SIM) IP
Measure the Signal Quality of Silicon Interconnects
The performance of high-speed interface and silicon interconnects such as UCIe, HBM, and other proprietary interfaces that use a clock forwarding scheme, are critical to monitor over the silicon lifecycle to ensure optimal system level performance.
Synopsys SLM Signal Integrity Monitor (SIM) IP enables an accurate measurement of these silicon interconnects with real time reporting for analytics. This real-time reporting enables structural lane monitoring and aging related degradation and optional repair (with the use of MTR), of failing lanes to maintain high-speed performance throughout the silicon lifecycle.
The SIM unit (SIMU) has a capture mode for reporting the positive and negative margin of signal edge relative to clock edge. It can support SDR and DDR formats with clock forwarding scheme. Typically, one SIMU is connected at the end of each lane and all the SIMUs form a chain connecting to the SIM controller (SIMC). SIMC provides control /status and test access via 1500/1687.
Figure 1: Synopsys SLM Signal Integrity Monitor (SIM) IP
Figure 2: Block Diagram of SLM SIM IP
Key Features
- SIMU + SIMC based complete solution for multi-die packages
- Distributed architecture with low overhead
- Available as hard IP integrated with PHY or soft IP with flexibility to customize
- EDA integration for automated insertion and connection
- Capture state of silicon precisely at any stage of its lifecycle
Key Benefits
- Health check of die-to-die interfaces within 3DIC
- Interface signal timing margin measurement
- Test and repair of PHY in-test or in-field
- Optimize silicon performance for safety critical applications
PODCASTS