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Synopsys Technology Access Program (TAP-in) promotes interoperability through open source licensing of interface formats. To access the following Synopsys formats, you must first register and accept the open source license agreement for each format you wish to download.

Interconnect Technology Format (ITF)
Provides detailed modeling of interconnect parasitic effects that enables designers to perform accurate parasitic extraction for timing, signal integrity, power and reliability signoff analysis.

Liberty
A gate-level modeling technology for timing, noise, power and test behavior that powers Synopsys Design Platform and sign-off tools. Learn more about Liberty and the Liberty Technical Advisory Board by visiting .

OpenMAST
A mixed-technology language for electromechanical design and analysis.

Synopsys Design Constraints (SDC)

Used to describe the "design intent" and surrounding constraints for synthesis, clocking, timing, power, test and environmental and operating conditions.

V-SDC
Used to streamline functional verification through the use of equivalency checking.