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When designers synthesize chip designs with aggressive PPA targets, the expectation and goal is to be able to complete verification with minimal effort and a fast turn-around-time. Synopsys Design Compiler and Fusion Compiler offer a broad spectrum of optimization techniques such as retiming, multibit banking and advanced data-path optimizations, though these techniques can end up being inconsequential if they cannot be verified through equivalence checking. Therefore, the ideal setup is completed quickly using equivalence checking to provide out-of-the-box results so lengthy iterations and engineer hours aren¡¯t spent converging on verification pass.

This presentation will detail how Synopsys Formality ML-driven Distributed Processing (DPX) delivered out-of-the-box verification for STMicroelectronics Design team without the need to scale back optimizations or sacrifice PPA goals. Attendees will walk away with an understanding of how Synopsys Formality equivalence checking captures the design transformation/optimizations in Formality Guide Files (SVF) for rapid setup of the verification environment to avoid multiple iterative runs. In addition, ML-driven adaptive distributed verification techniques will be highlighted, which help to partition the design and run solvers in parallel to further accelerate verification runtime and out-of-the-box results.