Synopsys Cloud
Cloud native EDA tools & pre-optimized hardware platforms
Request a Free Trial →
Synopsys Webinar | Watch On-Demand
In this ASIP Seminar learn why domain-specific processors (also referred to as application-specific processors, or ASIPs, for short) are getting a lot of attention these days, and why Synopsys¡¯ ASIP Designer is the industry¡¯s leading tool to design, implement, program, and verify such specialized processors. Whether you plan to start from a RISC-V ISA using one of the RISC-V example models that come with ASIP Designer, or you are considering replacing your fixed-function hardware accelerator with a more flexible yet efficient programmable accelerator, this seminar is for you.
Topics covered:
- An introduction to the ASIP Designer tool suite
- AI-RISC - Scalable RISC-V processor with tightly integrated AI accelerators and custom instruction extensions (Invited talk by the University of Virginia)
- Case study: Tmatch, a flexible stereo image matching accelerator designed with ASIP Designer
Speakers
Patrick Verbist
Product Manager
Synopsys Belgium
Patrick is the Product Manager for Synopsys¡¯ ASIP Designer tools. Previously he was Business Development Manager and Field Application Engineer for the ASIP Designer tools and, prior to the acquisition by Synopsys in 2014, Director of Sales at Target Compiler Technologies. Before Target, Patrick worked for 12 years as Business Development Manager for imec in Belgium and San Jose (US). He holds a Master¡¯s degree in Electrical Engineering from KU Leuven, Belgium
Falco Munsche
Technical Manager
Synopsys Germany
Falco is the Technical Manager for Synopsys' ASIP Designer tools. Previously he worked for a total of 20 years as Application Engineer and Software Engineer of ASIP design tools for Synopsys and CoWare, and as a Design Consultant for Synopsys. He holds a Ph.D. (2002) and Dipl-Ing. degree (1995) in Electrical Engineering from RWTH Aachen University.
Vaibhav Verma
PhD student at Electrical Engineering Department
University of Virginia
Vaibhav is a graduate student at University of Virginia pursuing Ph.D. in Electrical Engineering. He received his B.E. in Electrical and Electronics Engineering from Birla Institute of Technology and Science - Pilani, India in 2013. Before starting his graduate degree, he worked as R&D Engineer at Synopsys focusing on memory design in advanced technologies. He has held research internship positions at Central Electronics Engineering Research Institute, Synopsys and Qualcomm. His research interest lies in energy-efficient circuit design and high performance low-power hardware architectures for edge AI. His current research focuses on hardware/software co-design of a RISC-V based AI processor for energy-efficient processing of AI applications at the edge of IoT.
Mircea R. Stan
Professor, ECE Department
University of Virginia
Mircea received the Ph.D. (1996) and the M.S. (1994) degrees from UMass Amherst and the Diploma (1984) from the Polytechnic Institute in Bucharest, Romania. Since 1996 he has been with the ECE Department at UVa, where he is now the Virginia Microelectronics Consortium (VMEC) professor. Prof. Stan is teaching and doing research in the areas of high-performance low-power VLSI, temperature-aware circuits and architecture, embedded systems, spintronics, and nanoelectronics. He leads the High-Performance Low-Power (HPLP) lab, is an associate director of the Center for Automata Processing (CAP), and is on the leadership council for the Link Lab. He was a visiting faculty at UC Berkeley in 2004-2005, at IBM in 2000, and at Intel in 2002 and 1999. He received the 2018 Influential ISCA Paper Award (For 2003 paper "Temperature-aware microarchitecture"), the NSF CAREER award in 1997 and was a co-author on best paper awards at ASILOMAR19, LASCAS19, SELSE17, ISQED08, GLSVLSI06, ISCA03 and SHAMAN02 and IEEE Micro Top Picks in 2008 and 2003. He gave keynotes at DCAS18, SOCC16, CogArch16, WoNDP15, iNIS15 and CNNA14. He was the chair of the VSA-TC of IEEE CAS in 2005-2007, general chair for ISLPED06 and GLSVLSI04, TPC chair for SOCC18, ISVLSI17, NanoNets07 and ISLPED05, and on technical committees for numerous conferences. He is Associate Editor-in-Chief for the IEEE TVLSI, Senior Editor for the IEEE TNano, AE for IEEE Design & Test, and was an AE for the IEEE TNano in 2012-2014, IEEE TCAS I in 2004-2008 and for the IEEE TVLSI in 2001-2003. He was Guest Editor for the IEEE Computer special issue on Power-Aware Computing in December 2003 and a Distinguished Lecturer for the IEEE Circuits and Systems (CAS) Society in 2020-2021, 2012-2013 and 2004-2005, and for the Solid-State Circuits Society (SSCS) in 2007-2008. Prof. Stan is a fellow of the IEEE, a member of ACM, and of Eta Kappa Nu, Phi Kappa Phi and Sigma Xi. His h-index is 52 and his i10-index is 135.