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Abstract:
A successful multi-die design begins at the architecture exploration level. However, the architecture challenges are exacerbated for multi-die designs as performance and power need to be optimized across multiple heterogeneous and homogeneous dies. Disaggregating IPs based on workload demands, selecting the right interface, and accurately predicting power and performance indicators are among some of the key considerations at the early architecture level. The multi-die ecosystem must come together to collaborate on such considerations to optimize their multi-die designs.
Featured Speakers:
- Tim Kogel, Sr. Director, Technical Product Management, Synopsys
- Vikrant Kapila, Principal Engineer, Altera, an Intel Company
Learn About:
- A data-driven approach for early design space exploration to optimize resource allocation across multiple dies, accurately predict power and performance requirements, and make informed power and performance tradeoffs with the selected die-to-die interface
- How to reduce design iterations and accelerate time-to-market by scaling and optimizing resources to meet the needs of your multi-die design for the target application
- The successful results that were generated from this data-driven approach using Synopsys Platform Architect for Multi-Die and Intel Agilex Adaptive SoC
Watch On-Demand
Featured Speakers
Tim Kogel
Sr. Director, Technical Product Management, Synopsys
Tim received his PhD from RWTH Aachen in 2005 and has authored numerous publications on system-level modeling. Tim is leading a team of solution specialists, responsible for the definition, realization, and deployment of Synopsys¡¯ Virtual Prototyping solutions.
Vikrant Kapila
Principal Engineer, Altera, an Intel Company
Vikrant is a recognized expert in system architecture, power performance modeling, design space exploration (DSE), and optimizations. He serves as the lead NoC Architect and global performance lead for the SoC device family. His extensive expertise covers the entire solution stack, from DDR, HBM, NoC, and PCIe, to AI accelerators and system applications like AI, IPU (SmartNIC), and other networking applications.
