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Synopsys Webinar | Watch On-Demand
This Synopsys webinar shares real-life examples of how to execute clock gating verification with a well-defined methodology using the Synopsys VC Formal Sequential Equivalence Checking app. By the end of this Synopsys webinar, you will be able to uncover corner case clock gating bugs that are difficult to verify with simulation.
This is a two-part Synopsys webinar series intended to teach clock gating formal verification for any level user.
- Part 1 was prepared for engineers who are new to this area of expertise.
- Part 2 is for experienced RTL designers and verification engineers who want to design high-quality clock gating circuits and verify with confidence.
Guest presenter, Xiushan Feng, shares his more than 10 years¡¯ experience in this specific area to demonstrate how you can formally verify clock gating designs with a high confidence.
Speakers
Xiushan (Shaun) Feng
Principal Engineer
Samsung
Xiushan Feng is the leader of formal verification group at Samsung Austin R&D Center and San Jose Advanced Computing Lab. His team supports CPU and GPU projects within Samsung. He received a PhD degree in formal verification from University of British Columbia at Vancouver, Canada. Before joining Samsung, he led the formal verification efforts at Oracle Labs, Nvidia, Freescale, and AMD. Feng has 6 verification patents and has published more than 30 technical papers.
Sudipta Kundu
Principal R&D Engineer
Synopsys
Sudipta Kundu is a R&D Principal Engineer in the Verification Group at Synopsys. He is the R&D architect of the VC Formal Sequential Equivalence Checking (SEQ) App. He leads the R&D of various VC Formal Apps including SEQ, FSV, FXP, and FuSa. He received a B.S. and M.S. degree from IIT Kharagpur, India and a PhD in Computer Engineering from University of California San Diego. He has 1 book, 3 patents (4 pending) and published 12 peer-reviewed technical papers. His expertise includes equivalence checking, formal technologies, compilers and distributed systems.