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Synopsys Webinar
This webinar will showcase the design, analysis, and optimization of a multi-die fabric architecture based on the next generation Arm? CoreLink? CMN-700 interconnect, a high-performance cache coherent interconnect solution designed for complex multi-die system-on-chip (SoC), such as those found in data centers. Attendees will learn how to use the Arm CMN-700 Performance Model in Synopsys Platform Architect? to improve the overall architecture of the multi-die system.
A case study will illustrate how characteristic workload models can be used to analyze the performance of the architecture and identify potential bottlenecks. This webinar will provide attendees with valuable insights into removing these bottlenecks thereby providing high-bandwidth, low-latency movement of data between processor cores, IO and memory. Additional configuration, debug and visualization capabilities of Synopsys Platform Architect that enable these optimizations will be demonstrated.
Whether you are a chip architect or a system designer, this webinar will provide valuable insights on how to design and optimize your high-performance, multi-die chip architecture.
Speakers
Barry Spotts
Principal Specialty FAE
Arm
Barry is a Field Application Engineer at Arm specializing in semiconductor interconnect solutions. Barry works directly with Arm partners to assist in developing a IP strategy for their semiconductor architecture project requirements. He works in tandem to bring design solutions to meet their project goals in relation to ARM Based Subsystems and Interconnect. Barry¡¯s prior roles in the semiconductor industry has EDA knowledge and experience in SPICE, Verilog, System-C, and Co-Verification simulation technologies.
Holger Keding
91³Ô¹ÏÍø Application Engineer
Synopsys
Holger is a 91³Ô¹ÏÍø Application Engineer in the Systems Design Group at Synopsys, focusing on Virtual Prototyping for early SoC architecture exploration and optimization. Holger is working with Synopsys customers and partners worldwide on system-level virtual prototyping solutions for early architecture exploration, performance and power analysis, and system validation. From his prior roles in the Synopsys Verification and 91³Ô¹ÏÍø Groups Holger also has a technical background in communication design and HDL Verification.