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Overview
STMicroelectronics (ST), headquartered in Geneva, Switzerland, is a leading semiconductor company that develops chips for a wide range of industries, including automotive, industrial, consumer electronics, and the Internet of Things (IoT). To meet the increasing demands for system-on-chips (SoCs) that adhere to functional safety (FuSa) and security standards, ST designs custom processors that implement mechanisms to satisfy these requirements. One of the key tools in their arsenal is the Synopsys ASIP Designer, which has been instrumental in accelerating the design and verification of application-specific instruction-set processors (ASIPs).
"Synopsys ASIP Designer enables us to rapidly explore different instantiations of our dual core, which saves substantial time and effort while ensuring that we have a reliable design for safety-critical applications. The automated tool maximizes productivity of our engineering team, enabling us to meet our customers¡¯ time-to-market demands."
Anne Merlande
|Processor Architecture Expert, ST
"With the new DCLS features in Synopsys ASIP Designer, we can rapidly explore different RTL instantiations of our dual-core processors, saving substantial time and effort while ensuring that we have a reliable design for safety-critical applications."
Christophe Monat
|Manager of Computing and Compilers Center, ST
Challenges
Designing and verifying ASIPs involves several complex steps:
- Processor Architecture Definition: Engineering teams need to define the optimal processor architecture for the application.
- Hardware and Software Development: Developing the hardware implementation and the associated software development kit (SDK).
- Safety and Security Requirements: Ensuring that the design meets FuSa and security standards, particularly for high-reliability applications such as automotive and industrial sectors.
Solution
To address these challenges, STMicroelectronics extended the use of Synopsys ASIP Designer for their dual-core lockstep (DCLS) ASIPs:
- Automated Design and Verification: The ASIP Designer tool automates the design and verification process, reducing the turnaround time by 5x compared to traditional RTL design flows.
- Functional Safety Features: The tool includes highly configurable DCLS FuSa and security features, allowing engineers to model a single ASIP architecture at a higher level.
- Error Detection Code (EDC): ASIP Designer can automatically insert EDC logic near the processor registers to provide alerts for random faults, further increasing device reliability.
Results
The collaboration between STMicroelectronics and Synopsys led to significant improvements in designing and verifying ASIPs:
- Accelerated Turnaround Time: The ST team achieved a 5x reduction in design and verification time, meeting aggressive time-to-market demands.
- Enhanced Reliability: The DCLS architecture and EDC logic ensure that the processors are reliable for safety-critical applications.
- Automated RTL Generation: ASIP Designer¡¯s automatic generation of the C compiler, instruction set simulator, debugger, and RTL streamlines the design process.
The partnership between STMicroelectronics and Synopsys has paved the way for more design teams to leverage the benefits of ASIPs. By automating many of the design and verification steps, the Synopsys ASIP Designer tool helps overcome the time-to-market challenges associated with hand-coding RTL. This collaboration demonstrates how specialized processing can be made more accessible and efficient, supporting the development of intelligent and connected devices.
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