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Pre-Silicon Verification of Die-to-Die IP with Novel ESD Protection
All major foundries have adopted the programmable electrical rule checker (PERC) as the pre-silicon electrostatic discharge (ESD) signoff tool for IP and chip designs. This concept of rule checking works fine for most IP types, but for die-to-die IP, used in 3DIC designs, the PERC approach may not be appropriate.
Synopsys has introduced a novel form of ESD protection, in which active power clamps are abandoned. Instead, the clamping is realized by power decoupling capacitance, which enables power stabilization in normal operation and sufficient to meet the relatively low ESD targets valid for the internal die-to-die I/Os.
This white paper uses Synopsys PrimeESD to demonstrate the proof of concept for a novel protection method, proposing it as an essential supplement to PERC in designs containing die-to-die IP.
The paper also highlights
- Industry trends in 3DIC pitches and ESD targets
- Conventional and novel ESD protection methods
- Design details of the UCIe PHY used to validate the novel ESD protection concept
- Results of the Synopsys PrimeESD analysis