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Need for Multi-die Chiplets Interconnect
Key applications like cloud, AI, 5G, automotive, and high-performance computing (HPC) coupled with the rapidly changing physics and economics of semiconductor scaling are leading to diverse integration trends and new die-to-die use cases. Semiconductor chiplet packaging (multi-die) is helping integrators take a new approach to build scalable and modular designs.
Multi-die SoC architectures are enabling bigger, more powerful SoCs than can be achieved with monolithic designs and at a lower price point. It also enables better scalability and composability of products leading to faster time to market and higher flexibility to address multiple market segments. Die-to-die interfaces are a key enabler of the multi-die SoC trend. Die-to-die interface needs to provide a seamless interconnect between dies with the lowest latency and highest energy efficiency in order not to impact system performance.
Overview of Chiplet Standards
The OIF Extra Short Reach (XSR), Open Compute Project Bunch of Wires (BOW) and OpenHBI (OHBI), and Chip Alliance Advanced Interface Bus (AIB) are the alliances and standards for 2D and 2.5D package types. These standards provide bandwidth versus power tradeoffs with a primary focus on providing transport connectivity between chiplets.
UCIe Chiplet Standard
In March 2022 the newly formed Universal Chiplet Interconnect Express (UCIe?) organization announced the ratification of the UCIe specification. Synopsys is a contributing member of the UCIe organization bringing a unique perspective to the industry consortium as an industry leader for EDA and IP solutions.
UCIe covers the complete protocol stack as well as the physical layers so it can address the most relevant multi-die SoC use cases. In contrast, other standard efforts have mostly focused on the physical layer aspects of the interface. The UCIe specification is compelling for the performance metrics it proposes as measured by edge efficiency, power efficiency, and latency, which will play a major role in driving the adoption of standards. The following are the key protocol features of UCIe 1.0 from a chiplet interconnect standard perspective:
- Protocol layer definition for non-coherent and coherent die-to-die links
- Implements FLIT (flow control unit) to transport PCI Express? (PCIe?) and Compute Express Link (CXL) traffic over UCIe, and to be able to extend the existing software ecosystem
- Streaming mode with vendor-defined FLITs for custom protocols
- A first-of-its-kind signaling interface between different layers of the protocol
- FLIT aware die-to-die interface (FDI)
- Raw data die-to-die interface (RDI)
- Physical interconnect signaling interface with usage models for single module and multi-module
- Data rates up to 32 GT/s
- Standard package (x16 lanes) and advanced package (x64 lanes) with a channel reach of 25mm/2 mm
- Transfer mode as a serial with clock shared between chiplets
- Degraded width/rates of operation
- The main band interface for data path, sideband interface for control and bringing up
- Lane repair and Lane reversal features
- Larger channel lengths through UCIe Retimers
Unlike most of the other standards, UCIe provides software stacking along with the physical layer to realize key functional parameters. The figure below provides an overview of the UCIe stack and functional aspects at each layer.
Source: https://www.uciexpress.org/_files/ugd/0c1418_c5970a68ab214ffc97fab16d11581449.pdf
Considering the overall features, numerous topologies are possible for UCIe designs. The following are some DUT types representing downstream and upstream port:
? PHY DUT with RDI interface and UCIe physical interface
? Die-to-die DUT with RDI and FDI interfaces
? Retimer DUT with UCIe physical interface
? Full-stack with protocol, die-to-die and physical layer
These DUT types warrant a broader set of verification approaches to cater to IP to system-level use models.
Key Verification Challenges
Let us consider a UCIe full-stack DUT acting as a downstream port. The figure below provides an overview of a typical UCIe stack design for a downstream port with the capability of supporting streaming/PCIe/CXL traffic using a single stack or multiple stacks. The physical layer can be a single module or multi-module capable of a standard or advanced package. The exact features supported are negotiated during the initial linkup and discovery phase.
Following are the key verification aspects and challenges seen when verifying a multi-protocol, multi-stack, and multi-module DUT type:
? Device capability discovery and configuration settings of the DUT to match upstream port capabilities using sideband interfaces
? RDI, FDI, vLSM and link-state machines and transitions
? Assessment of retry mechanism behavior at the die-to-die layer
? Training, lane reversal, and lane repair features at UCIe physical layer
? Effective way of generating protocol layer traffic based on discovered capabilities
? Ensuring reliable traffic for PCIe/CXL raw modes or UCIe defined FLIT modes including integrity and data encryption by protocol layer
? End-to-end data integrity for custom protocols defined over the streaming mode of operation
? Overall protocol performance throughput based on physical layer lane width and whether data rate capabilities are meeting design expectations
Synopsys UCIe Protocol Verification Solution
Synopsys has been working with industry leaders to ensure support for UCIe features and use cases.
¡°Synopsys has a long history of working on industry-standard technologies such as PCIe, CXL, and now UCIe, which uses PCIe/CXL for the protocol layer. Having early implemented Verification IPs and tools for Simulation, Emulation, Prototyping, and Software Virtual modeling play an important role in increasing the design credibility of products supporting emerging standards. We look forward to Synopsys participation in the adoption of UCIe to drive an open ecosystem with chiplets,¡± said UCIe Chairman and Intel Senior Fellow, Dr. Debendra Das Sharma.
Synopsys offers verification IP (VIP) and test suites to early adopters of UCIe. Leveraging Synopsys¡¯ broad interconnect portfolio, adopters can perform early verification of their SoC design with Synopsys VIP. Standard features include:
? VIP operation modes to support different DUT types at each layer or at full-stack including PHY DUT/Retimer DUT
? Testbench interfaces with/without PCIe/CXL protocol stack to ease the traffic generation and focus on UCIe features of DUT
? API for initiating sideband service requests
? API for traffic generation
? Protocol checks and functional coverage at each layer of stack and signaling interfaces
? Scalable architecture to facilitate verification of single or multi-module PHYs
? Synopsys defined Interoperability test suite
As the target usage for UCIe is die-to-die interconnects, the payload that the chiplet RTL requires demands faster hardware-based pre-silicon solutions. Synopsys transactors based on Synopsys IP enable fast verification hardware solutions including Synopsys ZeBu? emulation systems and Synopsys HAPS? prototyping systems for validation use-cases.
Synopsys protocol verification solutions are natively integrated with the Synopsys Verification Family of products including Synopsys Verdi? debug and regression management and automation with Synopsys VC Execution Manager.
To learn more about Synopsys VIP and protocol solutions, please visit www.synopsys.com/vip
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