Synopsys Cloud
Cloud native EDA tools & pre-optimized hardware platforms
Request a Free Trial →
In today¡¯s world of smartphones and tablets, high speed data at low power consumption is becoming increasingly important. MIPI M-PHY supports multiple applications with high data bandwidth and low power consumption which makes it a popular specification for mobile devices. Applications like JEDEC UFS 3.0 and MIPI UniPro 1.8 now support MIPI M-PHY 4.1 which provides high speed data at a rate of nearly 11Gbps (HS_G4). To learn more about latest UFS and UniPro specifications read our previous blog ¡°High Speed Memory in Smart Phones: MIPI UniPro v1.8 for JEDEC UFS v3.0¡±. Data at such a high speed can lead to inter-symbol-interference (ISI). M-PHY provides a safety measure to prevent the loss of data at HS_G4. In this blog, we are going to talk about the ¡®ADAPT¡¯ feature and its advantages which were introduced in M-PHY 4.0.
High speed requires a large amount of control, precision, and numerous safety measures so that the desired outcome is successful. In digital communication, recovering high speed data at the receiver end requires additional circuits like an equalizer to nullify ISI and sample correct data at a high speed. As high speed HS_G4 was introduced in M-PHY 4.0 and later, ¡®ADAPT¡¯ patterns were also introduced to adjust the equalizer settings and nullify ISI at high speeds.
The term ¡®ADAPT¡¯ derives from the term adaptive equalizer, which uses fixed patterns to compare against the received data and adjust the equalizer settings. The mechanism of adaptive equalizer is explained below: ¨C
- Bit patterns used in an adaptive equalizer module are known as training sequences.
- The receiver must realize sequences well in advance, so that it can compare and optimize its settings for proper data reception.
- The most commonly used training sequences are pseudo random bit sequences (PRBS), for example PRBS9.
- For M-PHY, PRBS9 is initialized with all 1¡¯s (1_1111_1111) and output is collected on every 8th clock.
- The ¡®ADAPT¡¯ pattern consists of 650 bits which include Marker0 + PRBS9 pattern + 1¡¯b0.
The figure below shows the ¡®ADAPT¡¯ operation and state flow in a snapshot taken from Synopsys Verdi Protocol Analyzer natively integrated with VC Verification IP for MIPI M-PHY supporting the ¡®ADAPT¡¯ feature:
In a complete system, the master/protocol requests for ¡®ADAPT¡¯ pattern transmission by asserting the TX_ADAPT_REQ signal. PHY asserts TX_ADAPT_ACTIVE to indicate the start of the ¡®ADAPT¡¯ pattern on serial lines. The ¡®ADAPT¡¯ symbols enable the PHY to re-adjust equalizer parameters derived from received high speed symbols and sample the next data correctly. Completion of ¡®ADAPT¡¯ is indicated by de-asserting the TX_ADAPT_ACTIVE signal which tells the master/protocol layer that PHY is ready to accept data with new equalizer settings.
In short, high speed requires more control and safety measures. High speed data causes ISI and requires the equalizer circuit to sample data correctly. M-PHY has introduced the ¡®ADAPT¡¯ pattern for HS_G4 speed to realign the equalizer so that data can be sampled correctly.
Continue Reading
Blog
2 min read
/
Sep 12, 2024
Industry First Verification IP for Arm AMBA DTI-G
