Synopsys Cloud
Cloud native EDA tools & pre-optimized hardware platforms
Request a Free Trial →
Table of Contents
IP traffic has been growing at a rate many could not have imagined. Driven by expanding Internet users and devices that yield faster wireless and fixed broadband access, the expeditious ethernet data rate has now reached to 400G. From 1Gbps in 1997, to 10Gbps in 2004, 100 Gbps in 2010, it took a while for the next set up to 400 Gbps.
Steered by the ever-increasing internet traffic, there is always a need for more bandwidth.
Evolution of Ethernet
IEEE pulled the existing standards to frame a pathway to 400G. The 100 Gbps based on four parallel lanes of 25 Gbps was the starting point for 400G development.
However, a method to increase the serial rate was surely needed for 400G. The data rate of 400G with 16 x 25 Gbps parallel lanes would require 32 fibers per link for transmit and receive. Multiple parallel fibers solution was acceptable for short-distance links but not for longer cable lengths because of the following reasons:
? The number of transmission lines cannot be increased without a limit, because beyond a frequency, the signal transit time could not be equal for all signal lines.
? Another point to consider is the electromagnetic interference with other serial lines. The higher the frequency, the more the probability of interference.
? Lastly, the larger number of cables will drastically affect the cost for longer distances.
Progression to PAM4
50/100 Gbps lane rate was vital for reaching 400G. NRZ (Non-return to zero) greater than 28 Gb/s limits trace length and increases cost. This leads to the change of signal-encoding scheme. Up until now, all Ethernet standards had used a 2-level NRZ method for encoding a binary data stream into a transmittable electrical signal.
To attain a higher data rate, a 4-level encoding scheme, known as PAM4 was introduced, which effectively doubles the amount of data transmitted in the same amount of time.
As described in Figure 2, NRZ transfers a data bit by dividing the electrical signal into two voltage levels while, in PAM4 two binary bits are clubbed together and transmitted over 4 voltage levels of electrical signal. The serial data rate now moved to 50GBPL.
- 50GBPL originated in the 802.3cd and 802.3bs specification, which brought up the advanced interfaces:
- 50G K41/50G CR1 (50G over single lane)
- 100G kR2/100G CR2 (100G over two lanes)
- 200G KR4/200G CR4 (200G over four lanes)
- 400G KR8/400G CR8 (400G over eight lanes)
- Considering the facts below, 200G/400G Ethernet is only the beginning of what¡¯s yet to come:
Overall bandwidth for data centers grows by 20 times every four years - Data center power consumption doubles every two years
- Hardware upgrade cycles for data centers occur every two years
In the next decade, we could see ourselves using 800G and 1.6T Ethernet speeds or faster. To meet the increasing set of applications and bandwidth, IEEE 802.3 ck specification introduced the 100GPL connectivity which adds the following new interfaces to the ever-growing Ethernet standard:
- 400G CR4/400G KR4 (400G over 4 lanes)
- 200G CR2/200G KR2 (200G over 2 lanes)
- 100G CR1/100G KR1 (100G over 1 lane)
Electrical PHYs and interfaces based on 100 Gb/s electrical signaling will boost the bandwidth and reduce the data center costs.
As 200G and 400G Ethernet solutions become mature, the next generation of Ethernet will be 800G, and 1.6T Ethernet.
Introduction of 100G BaseP interface will reflect its usage in side specifications like FlexE. Flex E in essence allows scope for supporting all the variants of Ethernet 100G /400G/200G/50G PHY uptill now (Flex E Draft 2.1). With the advent of the 100G Base P interface these PHY interfaces will make their way into the family of the supported Ethernet PHY variants.
You can learn more about Synopsys VIP for Ethernet and source code UNH-IOL test suites here.
Continue Reading
Blog
2 min read
/
Sep 12, 2024
Industry First Verification IP for Arm AMBA DTI-G
