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The growth of datacenter, storage, automotive and other emerging market applications is driving the development of next-generation memory technologies ¨C DDR5, LPDDR5. Like their predecessors, the latest memory technologies also use DFI, a standard interface between memory controller and PHY, to reduce the integration cost and increase performance and data throughput efficiency. DFI also has evolved along with the memory technologies, and next generation DFI 5.0 is here to ensure higher performance in the systems using DDR5/LPDDR5. In this blog, we will discuss the new features of DFI 5.0 specification.

DFI defines signals, timing, and functionality required for efficient communication across the interface. The specification is developed for design of both memory controller and PHY, but does not place any restrictions on how the memory controller interfaces to the system design, or how the PHY interfaces to the DRAM devices.

In DFI 5.0, training mode has been completely transformed to be a PHY-independent training mode, there by the PHY trains the memory interface without involving the controller. Geardown mode also has been extended to 2N mode. A new signal dfi_2n_mode has also been added to support this behavior. There are other significant improvements in DFI 5.0 to reduce power consumption, and improve interoperability & interface communication.

WCK (Write Clock)

An LPDDR5 SDRAM utilizes two types of clock with different frequency. The frequency of WCK is four times or twice higher than the command clock. Signals are defined in DFI 5.0 interface to control the WCK synchronization sequence ¨C turning the WCK on, the toggle modes, the static states, and turning the WCK off.  The signals are sent from the controller to the PHY data slices and are phased signals defined by the data interface clock frequency ratio. The dfi_wck_en signal defines when the clock is enabled or disabled. The dfi_wck_toggle signal communicates the states of the WCK: STATIC_LOW, STATIC_HIGH, TOGGLE and FAST_TOGGLE.