91³Ô¹ÏÍø

Data is the new fuel powering critical use-cases for cloud /edge computing, and advances in AI. All aspects of data handling ¨C gathering, storing, moving, processing, and dispersing ¨C pose unique design implementation and verification challenges. The need for heterogenous computing has given exponential rise to application specific accelerators, pushing the industry to come up with a solution for efficient data handling and resource utilization. CXL is a processor interconnect protocol designed to support high bandwidth, low-latency interface from CPU to workload accelerators, maintaining memory coherency across heterogeneous devices, while addressing security needs of the user.

Verification and Validation Challenges around CXL Systems

CXL standard presents a blend of peripheral interconnect, memory, coherency, and security domains. Below are the important points to consider when approaching verification of CXL systems.

1. Need for System Level Compliance: Since it¡¯s an emerging standard with heterogenous components from multiple vendors, adherence of all the system components is necessary for the setup to be functional.
2. System Level Coverage at Pre-silicon: CXL reuses Gen5 infrastructure with special handling (CXL cache/mem semantics) for upstream-downstream memory accesses for CPU-Device pairs generating the need to cover realistic memory coherency scenarios in a system setup.
3. Shifting left Post-silicon Validation: Limited motherboards and hardware devices ready for production in post-silicon, narrow the scope of post-silicon validation. Pre-silicon to Post-silicon sanity using the real hardware devices early is essential to avoid silicon re-spin

Synopsys Advantage

Fusion of domain expertise is key for realizing CXL systems & Synopsys leverages several decades of expertise to provide a comprehensive offering for enabling development of CXL based designs for its users.  CXL Protocol Continuum from Synopsys ¨C is a comprehensive and complete solution spanning architecture exploration, system design and implementation, functional verification and acceleration, software development, system validation, compliance testing, and interoperability of complete system.

Synopsys has a strong participation in the CXL Consortium, and has been a leading partner in driving the adoption, contribution to CXL standards to enable a wide variety of system-based applications and giving early advantage for Interop testing of latest of the CXL-CV compliance tests on our continuum solutions. Synopsys is a leading provider of DesignWare CXL IPs and PHYs, including CXL 2.0 Integrity and Data Encryption (IDE) Security IP Module compliant with the defined CXL 2.0 IDE specification.