Cloud native EDA tools & pre-optimized hardware platforms
Synopsys offers a broad set of verification solutions for next generation Arm? AMBA? protocols, including AMBA5 CHI Issue D(CHI-D), and verification automation solutions including VC AutoTestbench for Testbench Generation and VC Autoperformance for Performance Verification of ARM based protocols, which designers have widely adopted and achieved numerous tape-out successes. We continue the rapid expansion of Synopsys¡¯ verification solutions for AMBA protocols and strengthen our leadership with our latest offering of VIP for AMBA ACE5 and AXI5, which are already in use by early adopters of the new specifications. Synopsys VIP for the AMBA5 CHI Issue D (CHI-D) specification enabled early customers and partners to extend the standard architecture for their next-generation coherent designs with new enhancements for increased performance. Let¡¯s dive down to understand more about the new features and latency optimization techniques available in AMBA5 CHI Issue D.
Coherency is the crux to most of the today¡¯s complex SoCs targeting wide range of applications, such as: mobile, networking, AI/machine learning, automotive, and data centers. CHI is built on the same coherency protocol that is used in AMBA 4 ACE. CHI operates on the concept of Nodes and Interfaces, rather than the Master/Slave paradigm used by previous AMBA protocols. A CHI master is termed as Request Node (RN), CHI slave is termed as Slave Node (SN). The CHI interconnect consists of one or more Home Nodes (HN).
Coherent Hub Interface, popularly known as CHI, is an Interface specification that is part of 5th generation of AMBA protocols (AMBA5) from ARM, released in 2013. AMBA5 CHI defines the interfaces for connection of fully coherent processors and dynamic memory controllers, to high performance, non-blocking interconnects i.e. Hubs. CHI ensures that the interconnect never becomes the bottleneck in a scalable system with large number of coherent CPUs.
CHI-D introduces the support for key ARM Architecture features, a series of performance improvement features, transaction latency improvement features, and Functional Safety (FuSa) features. All these features are aligned with the requirements for the next generation Mobile, Automotive, Infrastructure (Networking and Data Center) system on chips (SoCs).
Synopsys solution for AMBA5 CHI-D, provides performance metrics for latency and throughput analysis, configurable interconnect model, a reference verification platform and system level checks for protocol, data integrity and cache coherency. Built-in coverage and verification plans are also included to speed up verification coverage closure. In addition, VIP is natively integrated with the Synopsys Verdi? Protocol Analyzer debug solution as well as Synopsys Verdi? Performance Analyzer.
To learn more about Synopsys VIP and test suites for AMBA protocols, please visit