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Automate End-to-End Traceability, Implementation and Verification of Automotive SoC Design
Accelerate the end-to-end safety design cycle for SoCs by using the safety specification format (SSF) for automotive designs up to ASIL D. SSF is a command interface that describes safety intent, such as hardware safety mechanisms and their attributes, across different tools involved in functional safety activities. After being manually or automatically generated, SSF can be used in RTL generation and verification tools, and digital design tools, to ensure that safety requirements are met at every phase in the design cycle.
Key Benefits
Automate Safety Design to Ease ISO 26262 Compliance
Traditionally, engineers identify hardware safety mechanisms for their designs and then manually insert them into the RTL or netlist. After the design and verification process, they would confirm whether the safety goals have been achieved. They might use spreadsheets to track the hundreds or thousands of requirements, requiring substantial manual effort, with the potential for human error.
Automating this process by using SSF delivers an array of benefits:
- Improves traceability by automating time-consuming and error-prone steps such as RTL generation, analysis, verification, implementation, and creating work products and supporting evidence
- Reduces or eliminates labor-intensive custom tool scripting, which can degrade time-to-results and quality-of-results
- Provides scalability for Synopsys or third-party IP design re-use
- Extends to non-automotive applications, such as client-server and industrial IoT
Figure 1: SSF is generated by Synopsys TestMAX? FuSa, selected DesignWare? IP, and VC Functional Safety Manager,
or can be generated by the user.
Additional Resources
Blog
Forging a Safety-Aware Path for ASIL D Automotive Designs
Learn about SSF and how it eases the path to ISO 26262 compliance.
SNUG
ASIL D-Compliant SoC Design with Synopsys¡¯ Safety Specification Format (SSF)
On March 31, learn about SSF to automate functional safety aspects of the SoC design cycle.