Synopsys ARC 605 Processor Core
The Synopsys ARC? 605 processor core is ideal for embedded real-time processing where high speed and deterministic response is required. The 605 is widely licensed and silicon proven with hundreds of customer tapeouts, and is shipped in hundreds of millions of customer chips annually.
Designed for a broad range of embedded control functions within SoCs, the ARC 605 has a full 4GB addressing range and support for a Power Management Unit (PMU) that offers advanced power management capabilities. Based on a Harvard architecture the 605 features single-cycle close coupled memory (CCM) for both instruction and data spaces. The cacheless design provides fast and deterministic processor performance for embedded applications. User defined custom instruction extensions may be incorporated by the user to achieve even higher performance levels. The processor is implemented with the efficient ARCompact 16-/32-bit Instruction Set Architecture (ISA) that reduces code size by up to 40% compared to 32-bit-only instruction sets.
The Synopsys ARC 605 is highly configurable and can be quickly and easily customized for a specific application, so designer can include only the features that they need minimizing power consumption and cost, while maximizing performance. The 605 is supported by a full suite of software and hardware development tools. The suite includes the MetaWare Development Kit that generates highly efficient code ideal for embedded applications, the ARC simulators including xCAM and nSIM, and the ARChitect configuration tool.
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- Developed for embedded SoC applications
- Harvard architecture with 5-stage, 32-bit pipeline
- 32-bit address and data busses (4GB address space)
- 16 or 32 entry 32-bit general purpose register file, extendible to 60 registers
- 1 KB - 512 KB Instruction Close Coupled Memory (ICCM)
- 2 KB - 256 KB Data Close Coupled Memory (DCCM)
- Deterministic and real-time instruction execution
- Efficient ARCompact 16/32-bit instruction set
- AHB, AXI or BVCI peripheral bus interface
- 32-bit auxiliary register space with single-cycle data storage and retrieval
- Up to 32 user configurable interrupts
- Optional 16x16 and 32x32 multipliers
- Optional 32-bit barrel shifter
- Zero overhead loop counter
- Optional CRC, normalize, swap instructions
- Support for custom instruction extensions
- Supported by a full suite of development tools
- JTAG debug interface with multi-core debug support
- Delivered as synthesizable RTL source code (Verilog)
| Description: | ARC 605 32-bit processor core for low-end embedded applications |
| Name: | dwc_arc_605_core |
| Version: | 4.9b |
| ECCN: | 3E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | arc_ARC600_Series_bundle |
| Product Code: | 8022-0, 8023-0, 8024-0, 8025-0, 8045-0, 8046-0, 9839-0 |