Synopsys ARC-V RPX Series Functional Safety Processor IP
The Synopsys ARC-V? RPX-110 series functional safety (FS) processors, which include the RPX-110-FS, RPX-115-FS, RPX-110V-FS, and RPX-115V-FS processors simplify development of high-performance safety-critical applications and accelerate ISO 26262 certification for automotive system-on-chips (SoCs). The Automotive Safety Integrity Level (ASIL) D compliant processors feature a pre-verified dual-core lockstep implementation including an integrated safety monitor. Additionally, they offer the flexibility to operate in an independent ¡°hybrid¡± mode for ASIL B or non-automotive applications that demand higher performance from the same design.
The Synopsys ARC-V RPX-110 series FS processors are backed by comprehensive safety documentation, including FMEDA reports, and are supported by the ARC-V? MetaWare Toolkit for Safety. This toolkit includes a certified ASIL D compliant compiler, to generate ISO 26262 compliant code.
Synopsys ARC-V RPX-115V Safety Processor Block Diagram
Synopsys ARC-V RPX-100 Series Functional-Safety Processor IP Datasheet
- Dual-issue, 64-bit RISC-V processors for performance efficient host application
- Configurable solution to support both ASIL B (Single core mode) and ASIL D (Dual core lock step), as defined by ISO 26262
- Multicore processor versions: up to 16 CPU cores, 12 HW accelerators
- Per-core configurable in lockstep or hybrid mode: Up to 16x ASIL B or 8x DCLS (ASIL D) cores
- HW safety features: ECC, integrated user-programmable windowed watchdog timer, E2E for buses/data-path, RAS registers, lockstep and integrated safety monitors
- RVA22 and optionally RVA23 RISC-V profile compliant
- Virtualization support through H-extension
- Up to 64 KB L1 instruction and data cache, optional unified private L2 cache of size 1 MB (shared between main core and shadow core if ASIL D selected), up to 64 MB of L3 shared cluster cache