Synopsys ARC-V? RMX-500 Processors are based on the RISC-V instruction set architecture (ISA) and optimized for use in embedded applications where power & performance efficiency are key concerns. The DSP enhanced implementation (RMX-500D) adds DSP capability for applications such as IoT wearable devices where the combination of low power and signal processing are required to enable device performance and extend battery life.

The processors feature an efficient 5-stage Harvard architecture pipeline that provides excellent throughput for embedded applications.

The ARC-V RMX-500 features up to 64KB of Level 1 (L1) instruction & data cache and up to 2MB each of closely coupled instruction and data memories (CCM), maintain high code density and offer excellent performance within a very small footprint.

Synopsys ARC-V RMX-500 Block Diagram

Synopsys ARC-V RMX-500 Series Datasheet

Highlights

Family of 32-bit processors for low-power embedded applications
Based on the RISC-V ISA, leveraging standard 32-bit protocols (and extensions)
RISC and RISC + DSP 32-bit processors for low-power embedded applications (RMX-500D)
DSP instruction extensions (RMX-500D)
Easy DSP programming support with MetaWare C/C++ Compiler (RMX-500D)
Feature-rich DSP software library for easy algorithm programming
High degree of configurability
Support for custom instructions
Support for up to 64KB of L1 instruction and data caches
Support for up to 2 MB of closely coupled instruction and data memory and direct mapping of peripherals
Native Arm AMBA? AHB?, AHBLite? and AXI interfaces
Optional 32x32 or 16x16 single and multicycle multiplier
ECC/Parity support
Advanced Platform Level Interrupt Controller (APLIC) supporting up to 1023 wired interrupts
ARC Trace I/F provides real-time trace debugging features