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The Synopsys SD/eMMC Host Controller IP addresses the growing storage needs of mobile, consumer, IoT and automotive applications. The IP provides advanced features such as ADMA3 supporting the SD 6.0 and SDIO 4.10 specifications as well as Command Queuing Engine (CQE) supporting the SD 6.0 and eMMC 5.1 specifications. The IP also provides advanced high-performance 32- and 64-bit AXI interface to the SoC.

The IP architecture leverages power management techniques, making it ideal for low-power applications. The highly configurable and scalable IP is packaged with Synopsys coreConsultant tool and is optimized to reduce gate count and power consumption while ensuring compatibility with previous and future generation SD and eMMC standards.

A rigorous UVM-based verification methodology is applied to the Synopsys SD/eMMC Host Controller IP, consisting of directed tests and constrained random verification. The simulation-based verification is further augmented with FPGA hardware verification based on Synopsys¡¯ HAPS?-DX FPGA-based prototyping system. The FPGA development board is tested with all major SD cards, SDIO commands, and eMMC devices. The IP is in volume production and has been successfully implemented in a wide range of applications.

The latest encryption/decryption feature adds secure storage capabilities to Mobile and IoT SoCs. The host controller manages all transformations internal to itself and can interface with any standard eMMC device. With a super low latency design, the Mobile Storage Host controller carries out all crypto-tasks on-the-fly with popular algorithm schemes, AES-XTS and AES-CBC.

Synopsys SD/eMMC Host Controller IP Datasheet
Synopsys SD/eMMC PHY IP Datasheet