The multi-lane Synopsys Multi-Protocol 10G PHY IP is part of Synopsys�� high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency in battery-operated consumer and mobile applications. The multi-protocol 10G PHY is small in area and provides low active and standby power while exceeding signal integrity and jitter performance of the PCI Express 3.1, SATA 6G and Ethernet standards.

The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY incorporates advanced power saving features such as L1 sub-states in-conjunction with power gating in standby mode of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive to further save active power.

The PHY's Automatic Test Equipment (ATE) capabilities and optional wirebond packaging reduce the overall bill of materials (BOM) cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the Synopsys Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and accelerates time-to-market.

Synopsys Multi-Protocol 10G PHY IP Datasheet

Highlights

Products

Downloads and Documentation

Supports 1.25 Gbps to 10 Gbps data rates
Supports PCI Express 3.1, SATA 6G, SGMII
Supports x1 to x16 macro configurations
Superior signal integrity across lossy backplanes enabled by a high-performance analog front-end that includes adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)Low active and standby power consumption compared to competing solutions due to L1 sub-states, power gating and novel transmitter design
Spread Spectrum Clock (SSC)
Separate Reference Clock Independent SSC (SRIS)
Reference clock sharing for aggregated macro configurations
PCI Express Aggregation and bifurcation
Embedded bit error rate (BER) tester and internal eye monitor
Built-in self test (BIST) including 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker
Supports flip chip and wirebond packaging
Supports IEEE 1149.6 AC Boundary Scan
Supports -40C to 125C Tj

Multiprotocol 10G PHY, SS 8LPU x1, North/South (vertical) poly orientation	STARs	Subscribe
Multiprotocol 10G PHY, TSMC 16FFC x1, North/South (vertical) poly orientation	STARs	Subscribe
Multiprotocol 10G PHY, TSMC N7 x2, North/South (vertical) poly orientation	STARs	Subscribe
10G Multi-Protocol PHY, GF 22FDSOI x1, N/S, for Automotive, ASIL B Random, AEC-Q100 Grade 1	STARs	Subscribe
MP10, USB 3.1/PCIe 3.0 PHY, GF 22FFDSOI x1, N/S, for Automotive, ASIL B Random, AEC-Q100 Grade 1	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 16FFC x2, N/S, for Automotive, ASIL B Random, AEC-Q100 Grade 2	STARs	Subscribe
10G PHY for PCIe 2.0, TSMC 7FF x1, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 2.0, TSMC 7FF x2, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, GF 22FFDSOI X1, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, SS SF5 x1, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, SS SF5 x2, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 10FF x1, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 12FFC x1, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 12FFC x2, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 12FFC x4, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 16FFC x16, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 16FFC x1, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 16FFC x2, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 16FFC x4, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 16FFPGL x4, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 16FFPLL x1, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 16FFPLL x4, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 16FFPLL x8, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC N5 X1, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 7FF x1, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 7FF x2, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 7FF x4, North/South (vertical) poly orientation	STARs	Subscribe
10G MP PHY for PCIe 3.0/USXGMII/SGMII, TSMC 12FFC x1, North/South (vertical) poly orientation	STARs	Subscribe

Description:	10G MP PHY for PCIe 3.0/USXGMII/SGMII, TSMC 12FFC x1, North/South (vertical) poly orientation
Name:	dwc_mp10usxgmiiphy_tsmc12ffcx1ns
Version:	1.07a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10G Multi-Protocol PHY ATE Test Bench (ATE Version: 1.10a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare Cores Multi-Protocol 10G PHY x1 for TSMC12FFC (PHY Version: 1.07a) ( PDF \| HTML ) Multi-Protocol PCS for the DesignWare Cores Multi-Protocol PHY (PCS Version: 3.52b) ( PDF \| HTML ) Release Notes Multi-Protocol 10G PHY X1 for TSMC 12 FFC Release Notes (PHY Version: 1.07a) ( TEXT )
Download:	dwc_mp10usxgmiiphy_tsmc12ffcx1ns
Product Code:	D874-0

Description:	10G Multi-Protocol PHY, GF 22FDSOI x1, N/S, for Automotive, ASIL B Random, AEC-Q100 Grade 1
Name:	dwc_ap1_c10mpphy_gf22fdsoiext_x1ns
Version:	2.04e
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores 10G Multi-Protocol PHY ATE Test Bench (ATE Version: 1.00a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks Consumer Multi-Protocol PCS for the DesignWare Cores Multi-Protocol 10G PHY ( PDF \| HTML ) DesignWare Cores 10G Multi-Protocol PHY for GF 22FDSOI-EXT Databook (PHY Version: 2.04e) ( PDF \| HTML ) Release Notes DWC 10G Multi-Protocol PHY for GF 22FDSOI-EXT 1.8V Release Notes (PHY Version: 2.04e) ( TEXT )
Download:	dwc_ap1_c10mpphy_gf22fdsoiext_x1ns
Product Code:	F689-0

Description:	10G PHY for PCIe 2.0, TSMC 7FF x1, North/South (vertical) poly orientation
Name:	dwc_c10pcie2phy_tsmc7ff_x1ns
Version:	4.03b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10G PCIe 2 PHY ATE Test Bench (Doc Version: 1.70a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare Cores Consumer 10 PCIe 2.1 PHY for TSMC7FF (PHY Version: 4.03b) ( PDF \| HTML ) PCIe 2.1 PCS for the DesignWare Cores C10 PCIe 2.1 PHY (PCS Version: 3.54a) ( PDF \| HTML ) Release Notes DesignWare Cores Consumer 10 PCIe 2 PHY x1 NS for TSMC7FF 1.8V Release Notes (PHY Version: 4.03b) ( TEXT )
Download:	dwc_c10pcie2phy_tsmc7ff_x1ns
Product Code:	C374-0

Description:	10G PHY for PCIe 2.0, TSMC 7FF x2, North/South (vertical) poly orientation
Name:	dwc_c10pcie2phy_tsmc7ff_x2ns
Version:	2.08a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Documentation:	Show Documents... Hide Documents... Application Notes Designware Cores Consumer 10 PCIe 2 PHY ATE Test Bench ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks Consumer 10G PCIe 2 PHY for TSMC 7 FF ( PDF ) Consumer PCIe 2 PCS for the DesignWare Cores Consumer PCIe 2 PHY ( PDF \| HTML ) Release Notes DesignWare Cores Consumer 10 PCIe 2 PHY for TSMC 7 FF ( TEXT )
Download:	PCIe-20-PHY_TSMC_N7_x2
Product Code:	E183-0

Description:	10G PHY for PCIe 3.0, GF 22FFDSOI X1, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_gf22fdsoiext_x1ns
Version:	2.04c
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10G PCIe 3.1 PHY ATE Test Bench (Doc Version: 1.80a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks Consumer PCIe 3.1 PCS for the DesignWare Cores PCIe 3.1 PHY (PCS Version: 3.2.6) ( PDF \| HTML ) DesignWare Cores Consumer 10G PCIe3 PHY for GF 22FDSOI-EXT (PHY Version: 2.04c) ( PDF \| HTML ) Release Notes DesignWare Cores PCIe3 x1 NS for GF 22FDSOIEXT 1.8V (PHY Version: 2.04c) ( TEXT )
Download:	dwc_c10pcie3phy_gf22fdsoiext_x1ns
Product Code:	E187-0

Description:	10G PHY for PCIe 3.0, SS SF5 x1, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_ss5lpex1ns
Version:	2.01d
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes C10 Hardware Emulation Application Note ( PDF \| HTML ) DesignWare Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench x1 for SS5 Application Note (PHY Version: 2.01d) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks Consumer PCIe 3.1 PCS for the DesignWare Cores Consumer PCIe 3.1 x1 PHY (PHY Version: 2.01d) ( PDF \| HTML ) Synopsys PHY IP Consumer 10G PCIe 3.1 PHY for SS5LPE (PHY Version: 2.01d_d1) ( PDF \| HTML ) Release Notes DesignWare Cores Consumer 10G PCIe 3.1 PHY x1 NS for SS5LPE Readme ( TEXT )
Download:	dwc_c10pcie3phy_ss5lpex1ns
Product Code:	E824-0

Description:	10G PHY for PCIe 3.0, SS SF5 x2, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_ss5lpex2ns
Version:	2.03c
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores PCIe 3.1 PHY ATE Test Bench (Version: 1.00a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks Consumer PCIe 3.1 PCS for the DesignWare Cores Consumer PCIe 3.1 x2 PHY (PHY Version: 2.03c) ( PDF \| HTML ) DesignWare Cores Consumer 10G PCIe 3.1 PHY for SS5LPE (PHY Version: 2.03c) ( PDF \| HTML ) Release Notes PCIe 3.1 x2 NS PHY for SS5LPE 1.8V Release Notes (PHY Version: 2.03c) ( TEXT )
Download:	dwc_c10pcie3phy_ss5lpex2ns
Product Code:	F536-0

Description:	10G PHY for PCIe 3.0, TSMC 10FF x1, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc10ffx1ns
Version:	1.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes Designware Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench for TSMC16 ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Databooks Consumer PCIe 3.0 PCS for the DesignWare Cores Consumer PCIe 3.0 for TSMC16 PHY ( PDF ) DesignWare Cores Consumer 10 PCIe 3.0 PHY for TSMC 10 FF ( PDF ) Datasheets Synopsys IP for PCI Express Complete Solution Datasheet ( PDF ) Synopsys Multi-Protocol 10G PHY IP Datasheet ( PDF ) Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With Synopsys IP Portfolio ( PDF ) ��˼�Ƽ��о�Ƽ� ��о�Ƽ��˼�Ƽ��Synopsys IPϵ��ʵ��SSD�� ( PDF )
Download:	PCIe-30-PHY_C10_TSMC_10FF_x1
Product Code:	B942-0

Description:	10G PHY for PCIe 3.0, TSMC 12FFC x1, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc12ffcx1ns
Version:	1.07a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench Application Note (Doc Version: 1.70a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks Consumer 10G PCIe 3.1 PHY x1 for TSMC 12 FFC Databook (PHY Version: 1.07a) ( PDF \| HTML ) PCIe 3.1 PCS for the DesignWare Cores Consumer 10G PCIe 3.1 PHY (PCS Version: 3.52b) ( PDF \| HTML ) Datasheet Synopsys IP for PCI Express Complete Solution Datasheet ( PDF ) Release Notes Consumer 10G PCIe 3.1 PHY x1 for TSMC 12 FFC Release Notes (PHY Version: 1.07a) ( TEXT )
Download:	dwc_c10pcie3phy_tsmc12ffcx1ns
Product Code:	C478-0, F900-0

Description:	10G PHY for PCIe 3.0, TSMC 12FFC x2, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc12ffcx2ns
Version:	1.07a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench Application Note (Doc Version: 1.70a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare Cores Consumer 10G PCIe 3.1 PHY x2 for TSMC12FFC Databook (PHY Version: 1.07a)) ( PDF \| HTML ) PCIe 3.1 PCS for the DesignWare Cores Consumer 10G PCIe 3.1 PHY (PCS Version: 3.52c) ( PDF \| HTML ) Datasheet Synopsys IP for PCI Express Complete Solution Datasheet ( PDF ) Release Notes PCIe 3.0 PHY x2 NS for TSMC 12FFC 1.8V Release Notes (PHY Version: 1.07a) ( TEXT )
Download:	dwc_c10pcie3phy_tsmc12ffcx2ns
Product Code:	C479-0

Description:	10G PHY for PCIe 3.0, TSMC 12FFC x4, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc12ffcx4ns
Version:	1.07a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench Application Note (Doc Version: 1.70a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare Cores Consumer 10G PCIe 3.1 PHY for TSMC12FFC x4 (PHY Version: 1.07a) ( PDF \| HTML ) PCIe 3.1 PCS for the DesignWare Cores Consumer 10G PCIe 3.1 PHY (PCS Version: 3.52a) ( PDF \| HTML ) Datasheet Synopsys IP for PCI Express Complete Solution Datasheet ( PDF ) Release Notes Consumer PCIe 3.0 PHY for TSMC12FFC x4 NS 1.8V (PHY Version: 1.07a) ( TEXT )
Download:	dwc_c10pcie3phy_tsmc12ffcx4ns
Product Code:	C480-0

Description:	10G PHY for PCIe 3.0, TSMC 16FFC x1, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc16ffc_x1ns
Version:	1.10a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench Application Note (Doc Version: 1.70a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare Cores Consumer 10G PCIe 3.1 PHY for TSMC16FFC x1 (PHY Version: 1.10a) ( PDF \| HTML ) PCIe 3.1 PCS for the DesignWare Cores Consumer 10G PCIe 3.1 PHY (PCS Version: 3.52b) ( PDF \| HTML ) Datasheets Synopsys IP for PCI Express Complete Solution Datasheet ( PDF ) Synopsys Multi-Protocol 10G PHY IP Datasheet ( PDF ) Release Notes DesignWare Cores Consumer 10G PCIe 3.1 PHY for TSMC16FFC x1 Release Notes (PHY Version: 1.10a) ( TEXT ) Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With Synopsys IP Portfolio ( PDF ) ��˼�Ƽ��о�Ƽ� ��о�Ƽ��˼�Ƽ��Synopsys IPϵ��ʵ��SSD�� ( PDF )
Download:	dwc_c10pcie3phy_tsmc16ffc_x1ns
Product Code:	B988-0

Description:	10G PHY for PCIe 3.0, TSMC 16FFC x16, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc16ffc_x16ns
Version:	1.07a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes Designware Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench for TSMC16 ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Databook Consumer PCIe 3.0 PCS for the DesignWare Cores Consumer PCIe 3.0 for TSMC16 PHY ( PDF ) Datasheets Synopsys IP for PCI Express Complete Solution Datasheet ( PDF ) Synopsys Multi-Protocol 10G PHY IP Datasheet ( PDF ) Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With Synopsys IP Portfolio ( PDF ) ��˼�Ƽ��о�Ƽ� ��о�Ƽ��˼�Ƽ��Synopsys IPϵ��ʵ��SSD�� ( PDF )
Download:	PCIe-30-PHY_C10_TSMC_16FFC_x16
Product Code:	C420-0

Description:	10G PHY for PCIe 3.0, TSMC 16FFC x2, N/S, for Automotive, ASIL B Random, AEC-Q100 Grade 2
Name:	dwc_ap_c10pcie3phy_tsmc16ffc_x2ns
Version:	1.06a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Documentation:	Show Documents... Hide Documents... Application Notes Designware Cores Consumer 10 PCIe 3.1 PHY for TSMC16 FFC ATE Test Bench Application Note (PHY Version: 1.05a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks Consumer PCIe 3.0 PCS for the DesignWare Cores Consumer PCIe 3.0 PHY (PHY Version: 1.06a) ( PDF \| HTML ) DesignWare Cores 10G AP PCIe 3.0 PHY for TSMC16FFC Databook (PHY Version: 1.06a_d1) ( PDF \| HTML ) Datasheet Synopsys Multi-Protocol 10G PHY IP Datasheet ( PDF ) Release Notes DesignWare Cores Consumer 10G AP PCIe 3.0 PHY for TSMC16FFC Release Notes (PHY Version: 1.06a) ( TEXT ) Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With Synopsys IP Portfolio ( PDF ) ��˼�Ƽ��о�Ƽ� ��о�Ƽ��˼�Ƽ��Synopsys IPϵ��ʵ��SSD�� ( PDF ) White Paper IP for Centralized ADAS Domain Controllers ( PDF )
Download:	dwc_ap_c10pcie3phy_tsmc16ffc_x2ns
Product Code:	C085-0

Description:	10G PHY for PCIe 3.0, TSMC 16FFC x2, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc16ffc_x2ns
Version:	1.10a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench Application Note (Doc Version: 1.70a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare Cores Consumer 10G PCIe 3.1 PHY for TSMC16FFC x2 Databook (PHY Version: 1.10a) ( PDF \| HTML ) PCIe 3.1 PCS for the DesignWare Cores Consumer 10G PCIe 3.1 PHY (PCS Version: 3.52c) ( PDF \| HTML ) Datasheets Synopsys IP for PCI Express Complete Solution Datasheet ( PDF ) Synopsys Multi-Protocol 10G PHY IP Datasheet ( PDF ) Release Notes DesignWare Cores USB 3.1 SS+ PHY for TSMC16FFC x2 Release Notes (PHY Version: 1.10a) ( TEXT ) Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With Synopsys IP Portfolio ( PDF ) ��˼�Ƽ��о�Ƽ� ��о�Ƽ��˼�Ƽ��Synopsys IPϵ��ʵ��SSD�� ( PDF )
Download:	dwc_c10pcie3phy_tsmc16ffc_x2ns
Product Code:	C047-0

Description:	10G PHY for PCIe 3.0, TSMC 16FFC x4, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc16ffc_x4ns
Version:	1.10a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench Application Note (Doc Version: 1.70a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare Cores Consumer 10G PCIe 3.1 PHY for TSMC16FFC x4 Databook (PHY Version: 1.10a) ( PDF \| HTML ) PCIe 3.1 PCS for the DesignWare Cores Consumer 10G PCIe 3.1 PHY (PCS Version: 3.52a) ( PDF \| HTML ) Datasheets Synopsys IP for PCI Express Complete Solution Datasheet ( PDF ) Synopsys Multi-Protocol 10G PHY IP Datasheet ( PDF ) Release Notes DesignWare Cores Consumer 10G PCIe 3.1 PHY for TSMC16FFC x4 Release Notes (PHY Version: 1.10a) ( TEXT ) Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With Synopsys IP Portfolio ( PDF ) ��˼�Ƽ��о�Ƽ� ��о�Ƽ��˼�Ƽ��Synopsys IPϵ��ʵ��SSD�� ( PDF )
Download:	dwc_c10pcie3phy_tsmc16ffc_x4ns
Product Code:	B943-0

Description:	10G PHY for PCIe 3.0, TSMC 16FFPGL x4, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc16ffpgl_x4ns
Version:	1.05a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes Designware Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench for TSMC16 ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Databooks Consumer PCIe 3.0 PCS for the DesignWare Cores Consumer PCIe 3.0 for TSMC16 PHY ( PDF ) DesignWare Cores Consumer 10 PCIe 3.0 PHY for TSMC 16 FFPGL ( PDF ) Datasheets Synopsys IP for PCI Express Complete Solution Datasheet ( PDF ) Synopsys Multi-Protocol 10G PHY IP Datasheet ( PDF ) Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With Synopsys IP Portfolio ( PDF ) ��˼�Ƽ��о�Ƽ� ��о�Ƽ��˼�Ƽ��Synopsys IPϵ��ʵ��SSD�� ( PDF )
Download:	PCIe-30-PHY_C10_TSMC_16FFPGL_x4
Product Code:	A827-0

Description:	10G PHY for PCIe 3.0, TSMC 16FFPLL x1, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc16ffpll_x1ns
Version:	1.05bpatch1
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes Designware Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench for TSMC16 ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Databooks Consumer PCIe 3.0 PCS for the DesignWare Cores Consumer PCIe 3.0 for TSMC16 PHY ( PDF ) DesignWare Cores Consumer 10 PCIe 3.0 PHY for TSMC 16 FFPLL ( PDF ) Datasheets Synopsys IP for PCI Express Complete Solution Datasheet ( PDF ) Synopsys Multi-Protocol 10G PHY IP Datasheet ( PDF ) Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With Synopsys IP Portfolio ( PDF ) ��˼�Ƽ��о�Ƽ� ��о�Ƽ��˼�Ƽ��Synopsys IPϵ��ʵ��SSD�� ( PDF )
Download:	PCIe-30-PHY_C10_TSMC_16FFPLL_x1
Product Code:	B865-0

Description:	10G PHY for PCIe 3.0, TSMC 16FFPLL x4, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc16ffpll_x4ns
Version:	1.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes Designware Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench for TSMC16 ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Databooks Consumer PCIe 3.0 PCS for the DesignWare Cores Consumer PCIe 3.0 for TSMC16 PHY ( PDF ) DesignWare Cores Consumer 10 PCIe 3.0 PHY for TSMC 16 FFPLL ( PDF ) Datasheets Synopsys IP for PCI Express Complete Solution Datasheet ( PDF ) Synopsys Multi-Protocol 10G PHY IP Datasheet ( PDF ) Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With Synopsys IP Portfolio ( PDF ) ��˼�Ƽ��о�Ƽ� ��о�Ƽ��˼�Ƽ��Synopsys IPϵ��ʵ��SSD�� ( PDF )
Download:	PCIe-30-PHY_C10_TSMC_16FFPLL_x4
Product Code:	A859-0

Description:	10G PHY for PCIe 3.0, TSMC 16FFPLL x8, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc16ffpll_x8ns
Version:	1.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Datasheets Synopsys IP for PCI Express Complete Solution Datasheet ( PDF ) Synopsys Multi-Protocol 10G PHY IP Datasheet ( PDF ) Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With Synopsys IP Portfolio ( PDF ) ��˼�Ƽ��о�Ƽ� ��о�Ƽ��˼�Ƽ��Synopsys IPϵ��ʵ��SSD�� ( PDF )
Download:	PCIe-30-PHY_C10_TSMC_16FFPLL_x8
Product Code:	A860-0

Description:	10G PHY for PCIe 3.0, TSMC 7FF x1, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc7ff_x1ns
Version:	4.03b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench (Doc Version: 1.90a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Synopsys PHY IP PCIe 3 PHY ATE Test Bench (Doc Version: 2.10a) ( PDF \| HTML ) Databooks DesignWare Cores Consumer 10 PCIe 3.1 PHY for TSMC7FF (PHY Version: 4.03b) ( PDF \| HTML ) Synopsys PHY IP PCIe 3.1 PCS for PCIe 3.1 PHY PHY/PCS Wrapper Databook (PCS Version: 3.54j) ( PDF \| HTML ) Datasheet Synopsys IP for PCI Express Complete Solution Datasheet ( PDF ) Release Notes DesignWare Cores Consumer 10 PCIe 3.1 PHY x1 NS for TSMC 7FF 1.8V Release Notes (PHY: Version 4.03b) ( TEXT ) Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With Synopsys IP Portfolio ( PDF ) ��˼�Ƽ��о�Ƽ� ��о�Ƽ��˼�Ƽ��Synopsys IPϵ��ʵ��SSD�� ( PDF )
Download:	dwc_c10pcie3phy_tsmc7ff_x1ns
Product Code:	C476-0

Description:	10G PHY for PCIe 3.0, TSMC 7FF x2, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc7ff_x2ns
Version:	4.03b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench (Doc Version: 1.90a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Synopsys PHY IP PCIe 3 PHY ATE Test Bench (Doc Version: 2.10a) ( PDF \| HTML ) Databooks DesignWare Cores Consumer 10 PCIe 3.1 PHY x2 for TSMC7FF (PHY Version: 4.03b_d1) ( PDF \| HTML ) PCIe 3.1 PCS for the DesignWare Cores C10 PCIe 3.1 PHY (PCS Version: 3.54a) ( PDF \| HTML ) Datasheet Synopsys IP for PCI Express Complete Solution Datasheet ( PDF ) Release Notes PCIe 3.1 PHY x2 NS for TSMC7FF 1.8V Release Notes (PHY Version: 4.03b) ( TEXT ) Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With Synopsys IP Portfolio ( PDF ) ��˼�Ƽ��о�Ƽ� ��о�Ƽ��˼�Ƽ��Synopsys IPϵ��ʵ��SSD�� ( PDF )
Download:	dwc_c10pcie3phy_tsmc7ff_x2ns
Product Code:	C477-0

Description:	10G PHY for PCIe 3.0, TSMC 7FF x4, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc7ff_x4ns
Version:	4.03b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench for TSMC7FF (PHY Version 4.01a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks Consumer PCIe 3.1 PCS for the DesignWare Cores Consumer PCIe 3.1 PHY for TSMC7FF x4 (PHY Version: 4.01a) ( PDF \| HTML ) DesignWare Cores Consumer 10 PCIe 3.1 PHY for TSMC7FF x4 (PHY Version: 4.03b_d1) ( PDF \| HTML ) Datasheet Synopsys IP for PCI Express Complete Solution Datasheet ( PDF ) Release Notes DesignWare Cores C10 PCIe 3.1 PHY x4 NS for TSMC7FF 1.8V Release Notes (PHY Version: 4.03b) ( TEXT )
Download:	dwc_c10pcie3phy_tsmc7ff_x4ns
Product Code:	C605-0

Description:	10G PHY for PCIe 3.0, TSMC N5 X1, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc5ff_x1ns
Version:	4.01c
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10G PCIe 3 PHY ATE Test Bench (May 20, 2022) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP Compilation Using the LC and FC End-User Platform (Doc Version: 1.11a) ( HTML ) Synopsys PHY IP Consumer 10G Compilation Using the LC and FC End-User Platform (Doc Version: 1.11a) ( PDF ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks Consumer PCIe 3.1 PCS for the DesignWare Cores PCIe 3.1 PHY x1 (PCS Version: 3.55a) ( PDF \| HTML ) DesignWare Cores Consumer 10 PCIe 3.1 PHY for TSMC5FF x1 Databook (PHY Version: 4.01c) ( PDF \| HTML ) Reference Manual DesignWare Cores Consumer 10 PCIe 3.1 PHY for TSMC5FF x1 Reference Manual (PHY Version: 4.01c) ( PDF \| HTML ) Release Notes DWC PCIe 3.1 PHY x1 NS for TSMC 5FF 1.2V Release Notes (PHY Version: 4.01c) ( TEXT )
Download:	dwc_c10pcie3phy_tsmc5ff_x1ns
Product Code:	E457-0

Description:	MP10, USB 3.1/PCIe 3.0 PHY, GF 22FFDSOI x1, N/S, for Automotive, ASIL B Random, AEC-Q100 Grade 1
Name:	dwc_ap1_mp10usb31pcie3phy_gf22fdsoiextx1ns
Version:	2.05a
ECCN:	5A991.B
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10 USB3.1 PCIe3 PHY ATE Test Bench (Doc Version: 1.10a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks Consumer Multi-Protocol PCS for the DesignWare Cores Multi-Protocol 10G PHY (PCS Version 3.2.4) ( PDF \| HTML ) DesignWare Cores Consumer 10G Multi-Protocol USB3.1 PCIe3 PHY for GF 22FDSOI-EXT Databook (PHY Version: 2.05a) ( PDF \| HTML ) Release Notes DesignWare Cores Consumer MP USB 3.1 / PCIe 3 x1 for GF 22FDSOIEXT 1.8V Release Notes (PHY Version: 2.05a) ( TEXT )
Download:	dwc_ap1_mp10usb31pcie3phy_gf22fdsoiextx1ns
Product Code:	F045-0

Description:	Multiprotocol 10G PHY, SS 8LPU x1, North/South (vertical) poly orientation
Name:	dwc_10g_phy_ss8lpu_x1ns
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Contact Us for More Information

Description:	Multiprotocol 10G PHY, TSMC 16FFC x1, North/South (vertical) poly orientation
Name:	dwc_10g_phy_tsmc16ffc_x1ns
Version:	1.11a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP Consumer 10G Multi-Protocol PHY ATE Test Bench (ATE Version: 1.20a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations Application Note (Doc Version: 1.00a) ( PDF \| HTML ) Databooks Synopsys PHY IP Multi-Protocol PCS for the Multi-Protocol PHY (Version: 3.72d) ( PDF \| HTML ) Synopsys PHY IP Multi-Protocol for TSMC16FFC x1 Databook (PHY Version: 1.11a) ( PDF \| HTML ) Reference Manual Synopsys PHY IP Multi-Protocol for TSMC16FFC x1 Reference Manual (PHY Version: 1.11a) ( PDF \| HTML ) Release Notes Synopsys PHY IP Multi-Protocol for TSMC16FFC x1 Release Notes (PHY Version: 1.11a) ( TEXT )
Download:	dwc_10g_phy_tsmc16ffc_x1ns
Product Code:	J124-0

Description:	Multiprotocol 10G PHY, TSMC N7 x2, North/South (vertical) poly orientation
Name:	dwc_10g_phy_tsmc7ff_x2ns
Version:	4.04a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP Compilation Using the LC and FC End-User Platform (Doc Version: 1.11a) ( HTML ) Synopsys PHY IP Consumer 10G Compilation Using the LC and FC End-User Platform (Doc Version: 1.11a) ( PDF ) Synopsys PHY IP Consumer 10G Multi-Protocol PHY ATE Test Bench Application Note (Version: 1.20b) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations Application Note (Doc Version: 1.00a) ( PDF \| HTML ) Databooks Synopsys PHY IP Consumer 10G Multi-protocol PHY for TSMC7FF PHY Databook (PHY Version: 4.04a) ( PDF \| HTML ) Synopsys PHY IP Multi-Protocol PCS for Multi-Protocol PCS Databook (PCS Version: 3.54a) ( PDF \| HTML ) Reference Manual Synopsys PHY IP Consumer 10G Multi-protocol PHY for TSMC7FF Reference Manual (PHY Version: 4.04a) ( PDF \| HTML ) Release Notes Synopsys PHY IP Consumer 10G Multi-protocol PHY for TSMC7FF Release Notes (PHY Version: 4.04a) ( TEXT )
Download:	dwc_10g_phy_tsmc7ff_x2ns
Product Code:	G084-0