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Synopsys LPDDR5/4/4X PHY IP

The Synopsys LPDDR5/4/4X PHY is Synopsys¡¯ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-in-package applications requiring high-performance LPDDR5X, LPDDR5, LPDDR4, and LPDDR4X SDRAM interfaces operating at up to 6400 Mbps. With flexible configuration options, the LPDDR5/4/4X PHY can be used in a variety of mobile applications supporting LPDDR5X, LPDDR5 and/or LPDDR4/4X SDRAMs, precisely targeting the specific power, performance, and area (PPA) requirements of these systems.

Optimized for high performance, low latency, low area, low power, and ease of integration, the LPDDR5/4/4X PHY is provided as hardened IP components (macrocells) to facilitate the following types of signals:

  • Single-ended Command/Address (C/A) and Data (DQ) signals
  • Differential signals (clock, data strobe, and WCK signals)
  • CMOS logic-level based C/A signals

The macrocells include fully integrated IOs and are easily assembled into a variety of configurations supporting a wide range of SoC DRAM interface requirements. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB) that features Synopsys¡¯ unique firmware-based training capability. In addition to training the interface after boot-up, the PUB contains the configuration registers for the PHY, performs periodic delay line compensation against voltage and temperature drift, performs DRAM retraining, and facilitates ATE testing and interface diagnostics. The LPDDR5/4/4X PHY includes a DFI 5.0 interface to the memory controller and can be combined with the Synopsys LPDDR5/4/4X Controller for a complete DDR interface solution.

Synopsys LPDDR5/4/4X PHY IP Datasheet

 

Highlights
Products
Downloads and Documentation
  • Supports JEDEC standard LPDDR5X, LPDDR5, LPDDR4 and LPDDR4X SDRAMs
  • Support for data rates up to 6400 Mbps
  • Designed for rapid integration with Synopsys¡¯ LPDDR5/4/4X controller for a complete DDR interface solution
  • DFI 5.0 controller interface
  • PHY-independent, firmware-based training using an embedded calibration processor
  • Optional dual channel architecture for LPDDR5X/LPDDR5/4/4X modes, which facilitates two independent channels in less area versus two independent PHYs
  • Support for DFI-based low-power modes and lower-power sleep and retention modes
  • Support for up to 15 trained states/frequencies
  • Flexible implementation to support Package-On-Package (PoP) or discrete DRAM-on-PCB systems with optimized PHY architecture
  • Built-in anti-aging features to prevent effects of NBTI & HCI
LPDDR5/4/4X PHY - SS 14LPU for Automotive AEC-Q100 Grade 1STARs Subscribe
LPDDR5/4/4X PHY - GF 12LP+ for Automotive ASIL B Random, AEC-Q100 Grade 1STARs Subscribe
LPDDR5/4/4X PHY - TSMC N7 for Automotive, ASIL B Random, AEC-Q100 Grade 2STARs Subscribe
LPDDR5/4/4X PHY - GF 12LP+STARs Subscribe
LPDDR5/4/4X PHY - TSMC 12FFCSTARs Subscribe
LPDDR5/4/4X PHY - TSMC 16FFCSTARs Subscribe
LPDDR5/4/4X PHY - TSMC N5STARs Subscribe
LPDDR5/4/4X PHY - TSMC N6STARs Subscribe
LPDDR5/4/4X PHY - TSMC N7STARs Subscribe
Description: LPDDR5/4/4X PHY - GF 12LP+
Name: dwc_lpddr54_phy_gf12lpp18
Version: 1.00a
ECCN: 3E991/NLR
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: dwc_lpddr54_phy_gf12lpp18
Product Code: F758-0
Description: LPDDR5/4/4X PHY - GF 12LP+ for Automotive ASIL B Random, AEC-Q100 Grade 1
Name: dwc_ap1_lpddr54_phy_gf12lpp18
Version: 1.00a
ECCN: 3E991/NLR
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: dwc_ap1_lpddr54_phy_gf12lpp18
Product Code: H754-0
Description: LPDDR5/4/4X PHY - SS 14LPU for Automotive AEC-Q100 Grade 1
Name: dwc_ag1_lpddr54_phy_ss14lpu18
Version: 1.00a
ECCN: 3E991/NLR
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: dwc_ag1_lpddr54_phy_ss14lpu18
Product Code: F799-0, I370-0
Description: LPDDR5/4/4X PHY - TSMC 12FFC
Name: dwc_lpddr54_phy_tsmc12ffc
Version: 2.80a
ECCN: 3E991/NLR
STARs: Open and/or Closed STARs
myDesignWare: Unsubscribe
Product Type: DesignWare Cores
Documentation:
Download: dwc_lpddr54_phy_tsmc12ffc18
Product Code: D774-0
Description: LPDDR5/4/4X PHY - TSMC 16FFC
Name: dwc_lpddr54_phy_tsmc16ffc
Version: 2.30a
ECCN: 3E991/NLR
STARs: Open and/or Closed STARs
myDesignWare: Unsubscribe
Product Type: DesignWare Cores
Documentation:
Download: dwc_lpddr54_phy_tsmc16ffc18
Product Code: D773-0
Description: LPDDR5/4/4X PHY - TSMC N5
Name: dwc_lpddr54_phy_tsmc5ff12
Version: 3.00a
ECCN: 3E991/NLR
STARs: Open and/or Closed STARs
myDesignWare: Unsubscribe
Product Type: DesignWare Cores
Documentation:
Download: dwc_lpddr54_phy_tsmc5ff12
Product Code: E377-0
Description: LPDDR5/4/4X PHY - TSMC N6
Name: dwc_lpddr54_phy_tsmc6ff18
Version: 1.40a
ECCN: 3E991/NLR
STARs: Open and/or Closed STARs
myDesignWare: Unsubscribe
Product Type: DesignWare Cores
Documentation:
Download: dwc_lpddr54_phy_tsmc6ff18
Product Code: E562-0
Description: LPDDR5/4/4X PHY - TSMC N7
Name: dwc_lpddr54_phy_tsmc7ff18
Version: 3.20a
ECCN: 3E991/NLR
STARs: Open and/or Closed STARs
myDesignWare: Unsubscribe
Product Type: DesignWare Cores
Documentation:
Download: dwc_lpddr54_phy_tsmc7ff18
Product Code: D221-0
Description: LPDDR5/4/4X PHY - TSMC N7 for Automotive, ASIL B Random, AEC-Q100 Grade 2
Name: dwc_ap_lpddr54_phy_tsmc7ff18
Version: 2.50a
ECCN: 3E991/NLR
STARs: Open and/or Closed STARs
myDesignWare: Unsubscribe
Product Type: DesignWare Cores
Documentation:
Download: dwc_ap_lpddr54_phy_tsmc7ff18
Product Code: D771-0