Enhanced Universal DDR Memory and Protocol Controllers
The Synopsys Enhanced Universal DDR Controllers consist of two high-performance products: the Enhanced Universal DDR Memory Controller (uMCTL2), and the Enhanced Universal DDR Protocol Controller (uPCTL2). Both products support the JEDEC DDR4, DDR3, DDR2, Mobile DDR, LPDDR4, LPDDR3, and LPDDR4 SDRAM standards and AMBA AXI3/AXI4 and native on-chip busses. Both products have extensive features for low power and high Reliability, Availability and Serviceability (RAS).
The uMCTL2 Memory Controller incorporates a scheduler and optional arbiter to serve memory requests from 1-16 application-side host ports with high bandwidth and low latency that is managed by Quality of Service (QoS) mechanisms.
The uPCTL2 Protocol Controller serves the needs of applications where scheduling is done in the interconnect or elsewhere on the host side, providing low latency and in-order command execution.
All the Synopsys Universal controllers connect to PHYs via the industry-standard DFI interface, and all their registers may be accessed through industry-standard APB busses.
Read more on the Synopsys blog, and the white papers, "Achieve 10X DRAM Bandwidth Improvement with a DDR Controller Read Reorder Buffer“ and “Reliability, Availability and Serviceability (RAS) for Memory Interfaces.”
Synopsys DDR Complete Solution Datasheet Synopsys Enhanced Universal DDR Memory and Protocol Controller IP Datasheet
- Select a complete multi-ported Enhanced Universal DDR Memory Controller offering 1 to 16 host ports, or join a third-party scheduler to a single-port Enhanced Universal Protocol Controller
- Support for JEDEC standard DDR2, DDR3, DDR4, LPDDR/Mobile DDR, LPDDR2, LPDDR3, and LPDDR4 SDRAMs
- Compatible with all Synopsys DDR PHYs (excluding DDR2/DDR PHYs) using DFI-compliant interfaces
- Multichannel and Shared Address/Command (Shared AC) configuration options
- Boot-time programmable frequency ratio
- Data rates up to 4266 Mbps in 1:2 frequency ratio, using a 1067 MHz controller and 2133 MHz memory clock (Dependent on process and PHY chosen)
- Data rates up to 3200 Mbps in 1:2 frequency ratio, using an 800 MHz controller clock and 1600 MHz memory clock (Dependent on process and PHY chosen)
- Data rates up to 1600 Mbps in 1:1 frequency ratio, using an 800 MHz controller clock and 800 MHz memory clock (Dependent on process and PHY chosen)
| Performance Enhanced version of uMCTL2 supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3 and LPDDR2 for Automotive | STARs | Subscribe |
| Performance Enhanced version of DDR Enhanced Memory Ctl (uMCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2 | STARs | Subscribe |
| DDR Enhanced Protocol Controller (uPCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2 | STARs | Subscribe |
| Description: | DDR Enhanced Protocol Controller (uPCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2 |
| Name: | dwc_ddr_upctl2 |
| Version: | 3.91a |
| ECCN: | 3E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Unsubscribe |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Toolsets: | Qualified Toolsets |
| Download: | dw_iip_DWC_ddr_umctl2 |
| Product Code: | B624-0 |
| Description: | Performance Enhanced version of DDR Enhanced Memory Ctl (uMCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2 |
| Name: | dwc_ddr_umctl2p |
| Version: | 3.91a |
| ECCN: | 3E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Unsubscribe |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Toolsets: | Qualified Toolsets |
| Download: | dw_iip_DWC_ddr_umctl2 |
| Product Code: | D854-0 |
| Description: | Performance Enhanced version of uMCTL2 supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3 and LPDDR2 for Automotive |
| Name: | dwc_ap_ddr_umctl2p |
| Version: | 3.91a |
| ECCN: | 3E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Unsubscribe |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dw_iip_ap_DWC_ap_ddr_umctl2 |
| Product Code: | E118-0 |