Description: | Synchronous Write-Port, Asynchronous Dual Read-Port RAM (Latch-Based) |
Name: | DW_ram_2r_w_s_lat |
Version: | DWBB_202409.1 |
ECCN: | EAR99/NLR |
STARs: | Open and/or Closed STARs |
myDesignWare: | Subscribe for Notifications |
Product Type: | DesignWare Building Blocks |
Overview: | DesignWare Building Block Components |
Documentation: | |
Examples: | Direct Instantiation in Verilog Direct Instantiation in VHDL |