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Synopsys Webinar | Available On Demand
When designers synthesize chip designs with aggressive PPA targets, the expectation and goal is to be able to complete verification with minimal effort and a fast turn-around-time. Synopsys Design Compiler and Fusion Compiler offer a broad spectrum of optimization techniques such as retiming, multibit banking and advanced data-path optimizations, though these techniques can end up being inconsequential if they cannot be verified through equivalence checking. Therefore, the ideal setup is completed quickly using equivalence checking to provide out-of-the-box results so lengthy iterations and engineer hours aren¡¯t spent converging on verification pass.
This presentation will detail how Synopsys Formality ML-driven Distributed Processing (DPX) delivered out-of-the-box verification for STMicroelectronics Design team without the need to scale back optimizations or sacrifice PPA goals. Attendees will walk away with an understanding of how Synopsys Formality equivalence checking captures the design transformation/optimizations in Formality Guide Files (SVF) for rapid setup of the verification environment to avoid multiple iterative runs. In addition, ML-driven adaptive distributed verification techniques will be highlighted, which help to partition the design and run solvers in parallel to further accelerate verification runtime and out-of-the-box results.
Speakers
Listed below are the industry leaders scheduled to speak.
Nathalie M¨¦loux
Principal Engineer
STMicroelectronics
Nathalie M¨¦loux, Principal Engineer at STMicroelectronics, has been working in the microcontroller division for over 20 years. She has greatly contributed to the development of the STM32 microcontrollers families since its inception. Nathalie has extensive experience in the areas of digital design methodology and low-power implementation flow. She is in charge of the digital flow, the support of the design implementation from RTL through Synthesis to P&R including signoff timing analysis, equivalence checking, power analysis and optimizations all along the flow.
Nathalie Meloux holds a master¡¯s degree in Microelectronics and Robotics from Polytech Montpellier, France and a D.E.A. (post-Master¡¯s degree) in Microelectronics from the University of Montpellier (Faculty of Science), France.
Stephane Maulet
Applications Engineer, Sr Staff
Synopsys
Stephane Maulet is a Senior Staff Applications Engineer at Synopsys. He has almost 20 years of experience in Synopsys front-end tools spanning Synopsys Design Compiler, Synopsys Fusion Compiler, Synopsys Formality and Synopsys Formality ECO.
Stephane holds a master¡¯s degree in Microelectronics Engineering from Grenoble INP, France.
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